Abstract: An integrated circuit includes first and second gate stacks located over a dielectric layer that is in turn disposed over a semiconductor substrate. Each gate stack includes a floating gate located on the dielectric layer and a control gate located over the floating gate. A first select gate electrode is located on a side of the first gate stack and a second select gate electrode is located on a side of the second gate stack. The first and second select gate electrodes have adjacent sidewalls, each adjacent sidewall having a rounded top corner. The gate stacks may be portions of a split gate memory cell.

Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.