Abstract: A load distribution device is configured to be placed against a region of interest of a patent that is susceptible to damage when placed against a support surface for a prolonged period of time. The load distribution device is placed against the patient such that the region of interest is aligned with an aperture of the load distribution device. The load distribution device can surround the region of interest. Thus, anatomical loading that might otherwise act against the region of interest instead is redistributed to a region of the patent that is adjacent the region of interest, and aligned with the body of the load distribution device.

Abstract: Various systems and methods for implementing intent-based cluster administration are described herein. An orchestrator system includes: a processor; and memory to store instructions, which when executed by the processor, cause the orchestrator system to: receive, at the orchestrator system, an administrative intent-based service level objective (SLO) for an infrastructure configuration of an infrastructure; map the administrative intent-based SLO to a set of imperative policies; deploy the set of imperative policies to the infrastructure; monitor performance of the infrastructure; detect non-compliance with the set of imperative policies; and modify the administrative intent-based SLO to generate a revised set of imperative policies that cause the performance of the infrastructure to be compliant with the revised set of imperative policies.

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and circuitry to: based on a configuration of operation specifying a standalone operation, cause the network interface device to operate in standalone to execute one or more applications and based on a configuration of operation specifying a companion operation, cause the network interface device to operate in companion to provide at least one host system with access to one or more hardware resources accessible by the network interface device.

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Abstract: Various systems and methods for implementing intent-based cluster administration are described herein. An orchestrator system includes: a processor; and memory to store instructions, which when executed by the processor, cause the orchestrator system to: receive, at the orchestrator system, an administrative intent-based service level objective (SLO) for an infrastructure configuration of an infrastructure; map the administrative intent-based SLO to a set of imperative policies; deploy the set of imperative policies to the infrastructure; monitor performance of the infrastructure; detect non-compliance with the set of imperative policies; and modify the administrative intent-based SLO to generate a revised set of imperative policies that cause the performance of the infrastructure to be compliant with the revised set of imperative policies.

Abstract: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS).

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

Abstract: Technologies for using a hardware queue manager as a virtual guest to host networking interface include a compute node configured to receive a pointer corresponding to each of one or more available receive buffers from a guest processor core of at least one processor of the compute node that has been allocated to a virtual guest managed by the compute node. The compute node is further configured to enqueue the received pointer of each of the one or more available receive buffers into an available buffer queue and facilitate access to the available receive buffers to at least a portion of a plurality of virtual switch processor cores. Each of the virtual switch processor cores comprises another processor core of the plurality of processor cores that has been allocated to a virtual switch of the compute node. Other embodiments are described herein.

Abstract: Examples may include a method of power aware load balancing in a computing platform. The method includes computing a number of enabled worker cores to process an expected traffic of received packets. A number of active consumer queues is adjusted based at least in part on the number of enabled worker cores, with consumer queues being associated with worker cores. A worker core polls the consumer queue associated with the worker core, gets and processes a packet descriptor describing a received packet from the consumer queue based on the consumer queue being not empty, and enters a low power state when the consumer queue is empty and pends on a new packet descriptor being entered into the consumer queue.

Abstract: A status assembly to provide visual and electronic indication of the position (open, closed, in-between) of the ram of a ram-type blowout preventer (BOP). The assembly is capable of coupling with a hydraulic motor that can be used to open and close the ram locks. The status assembly includes a rotatable element protruding from the BOP, a gear rotatable by the rotatable element, and an indicator that indicates the rotation position of the rotatable element and thus the linear position of the BOP ram. Some embodiments can also include a sensor that outputs an electronic signal to the system operator and can be incorporated into the main display for the BOP control system. This device is able to give immediate feedback to operators and to indicate whether each ram has achieved its intended travel.

Abstract: A status assembly to provide visual and electronic indication of the position (open, closed, in-between) of the ram of a ram-type blowout preventer (BOP). The assembly is capable of coupling with a hydraulic motor that can be used to open and close the ram locks. The status assembly includes a rotatable element protruding from the BOP, a gear rotatable by the rotatable element, and an indicator that indicates the rotation position of the rotatable element and thus the linear position of the BOP ram. Some embodiments can also include a sensor that outputs an electronic signal to the system operator and can be incorporated into the main display for the BOP control system. This device is able to give immediate feedback to operators and to indicate whether each ram has achieved its intended travel.

Abstract: A status assembly to provide visual and electronic indication of the position (open, closed, in-between) of the ram of a ram-type blowout preventer (BOP). The assembly is capable of coupling with a hydraulic motor that can be used to open and close the ram locks. The status assembly includes a rotatable element protruding from the BOP, a gear rotatable by the rotatable element, and an indicator that indicates the rotation position of the rotatable element and thus the linear position of the BOP ram. Some embodiments can also include a sensor that outputs an electronic signal to the system operator and can be incorporated into the main display for the BOP control system. This device is able to give immediate feedback to operators and to indicate whether each ram has achieved its intended travel.

Abstract: A status assembly to provide visual and electronic indication of the position (open, closed, in-between) of the ram of a ram-type blowout preventer (BOP). The assembly is capable of coupling with a hydraulic motor that can be used to open and close the ram locks. The status assembly includes a rotatable element protruding from the BOP, a gear rotatable by the rotatable element, and an indicator that indicates the rotation position of the rotatable element and thus the linear position of the BOP ram. Some embodiments can also include a sensor that outputs an electronic signal to the system operator and can be incorporated into the main display for the BOP control system. This device is able to give immediate feedback to operators and to indicate whether each ram has achieved its intended travel.

Abstract: A hydraulic blowout preventer operator comprises a piston rod having one end coupled to a closure member. The operator further comprises an operator housing having one end coupled to a bonnet and a second end coupled to a head. The piston rod extends through the bonnet into the operator housing where it is coupled to a piston that is disposed within the operator housing. The piston comprises a body and a flange. A flange seal is disposed on the flange and is sealingly engaged with the operator housing. A body seal is disposed on the body and is sealingly engaged with the operator housing. The flange seal has a sealing diameter greater than a sealing diameter of the body seal.

Abstract: A blowout preventer operator locking system comprises a piston rod having one end coupled to a closure member. The operator further comprises an operator housing having one end coupled to a bonnet and a second end coupled to a head. The piston rod extends through the bonnet into the operator housing where it is coupled to a piston that is disposed within the operator housing. The piston comprises a body and a flange. A sleeve is slidingly disposed within a cavity disposed within the piston and is rotationally fixed relative to the piston. A lock rod is rotatably coupled to the head and is threadedly engaged with the sleeve so that rotation of the lock rod axially translates the sleeve relative to the piston.

Abstract: A method for communicating between an application and a database by using a lightweight stored procedure data-binding framework for applications written in object oriented programming languages such as JAVA, significantly reduces the coding effort required to communicate with a relational database. Once the developer specifies the needed tabular data, the inventive framework generates all needed data objects and stored procedures to accomplish the interaction with that database data. The automatically generated code is then used by the application via a run-time component. This means the developer need only make simple calls in a few lines of code for database interaction. The encapsulated data model deals only with persistence and retrieval issues and is therefore de-coupled from the business model.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.