Patents by Inventor John Mark Boyer

John Mark Boyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11048292
    Abstract: An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 29, 2021
    Assignee: NXP USA, INC.
    Inventors: Anis Mahmoud Jarrar, John Mark Boyer, Nancy Hing-Che Amedeo
  • Publication number: 20200192419
    Abstract: An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Anis Mahmoud JARRAR, John Mark BOYER, Nancy Hing-Che AMEDEO
  • Patent number: 6167484
    Abstract: A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: December 26, 2000
    Assignee: Motorola, Inc.
    Inventors: John Mark Boyer, William Clayton Bruce, Jr., Grady Lawrence Giles, Thomas K. Johnston, Bernard J. Pappert, John J. Vaglica