Abstract: Stimulation signals (22) are applied to a first circuit model (20) and the power behaviour of the circuit being modelled is determined from the behaviour of the first circuit model (20). In parallel, the same stimulation signals (22) are applied to a second circuit model (26) and the state variable changes within that second circuit model are calculated. The calculated power behaviour and the calculated state variable changes are then applied as training data inputs to a self learning power model, such as a neural network (28), which learns the relationship between state variable changes between the second model (26) and power behaviour of the circuit being simulated. In this way, a detailed first circuit model (20) may be used to calculate power behaviour and to train a separate power model (28, 30) which once trained can be publicly released without having to release sensitive information within the first circuit model (20).

Abstract: A first model (10), such as a architectural level model or an instruction set simulator model makes calls to a second model (12), such as a pipeline simulator for a data processing device returning cycle count or energy consumption values. The calls to the second model are relatively slow. The system stalls the returned behavioural characteristics from the second model (12) in a memo table (14) and when a sufficient number of these have been returned with sufficiently little variation between them, then they are marked as being valid for use in place of a call to the second model (12), thus speeding up modelling.

Abstract: A software simulation technique for pipelined hardware is provided in which the hardware is modelled as a plurality of pipelined circuit element models that each respectively read their input data values from a first data storage area A and write their output data values to a second data storage area B. At the end of each simulated clock signal cycle, the first data storage area A and the second data storage area B are swapped to effectively replicate the behavior of the passing of signal values between pipelined stages in a hardware pipeline.

Abstract: A first model (10), such as a architectural level model or an instruction set simulator model makes calls to a second model (12), such as a pipeline simulator for a data processing device returning cycle count or energy consumption values. The calls to the second model are relatively slow. The system stalls the returned behavioural characteristics from the second model (12) in a memo table (14) and when a sufficient number of these have been returned with sufficiently little variation between them, then they are marked as being valid for use in place of a call to the second model (12), thus speeding up modelling.

Abstract: Stimulation signals (22) are applied to a first circuit model (20) and the power behaviour of the circuit being modelled is determined from the behaviour of the first circuit model (20). In parallel, the same stimulation signals (22) are applied to a second circuit model (26) and the state variable changes within that second circuit model are calculated. The calculated power behaviour and the calculated state variable changes are then applied as training data inputs to a self learning power model, such as a neural network (28), which learns the relationship between state variable changes between the second model (26) and power behaviour of the circuit being simulated. In this way, a detailed first circuit model (20) may be used to calculate power behaviour and to train a separate power model (28, 30) which once trained can be publicly released without having to release sensitive information within the first circuit model (20).

Abstract: A software simulation technique for pipelined hardware is provided in which the hardware is modelled as a plurality of pipelined circuit element models that each respectively read their input data values from a first data storage area A and write their output data values to a second data storage area B. At the end of each simulated clock signal cycle, the first data storage area A and the second data storage area B are swapped to effectively replicate the behavior of the passing of signal values between pipelined stages in a hardware pipeline.