Abstract: An apparatus may include a processor configured to synthesize a first configuration file associated with a target field-programmable gate array (FPGA), and a second configuration file associated with the target FPGA, wherein first look-up-table (LUT) bits of the first configuration file are the logical inverse of second LUT bits of the second configuration file, and first non-LUT bits of the first configuration file are the same as second non-LUT bits of the second configuration file, and generate a LUT mask indicating which bits of the first configuration file and the second configuration file correspond to the first LUT bits and the second LUT bits by performing a bit-wise exclusive OR operation between the first configuration file and the second configuration file.

Abstract: A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.