Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract: A transformer comprises a printed circuit board having elongated conductors printed thereon, a ferrite core having a bottom mounted onto the printed circuit board and a flex circuit. The flex circuit comprises a dielectric sheet and elongated conductors printed on both faces of the sheet. The flex circuit is contoured around a top and sides of the core. The conductors of the flex circuit are surface bonded to respective conductors of the printed circuit board to form a series of primary windings and a series of secondary windings around the core. Provision of the upper portions of the windings by means of the flex circuit is economical because it does not require handling of discrete conductor portions.

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract: An aperture in an electronic substrate is filled with a filling material without need for a specially built fill mask. A layer of tape or tentable photosensitive dielectric film is applied to one surface of the substrate covering the aperture. An opening is made in the tape or film by directing radiation through the aperture. Fill material is then forced through the opening to substantially fill the aperture. Protruding nubs may be removed to planarize the substrate surfaces.

Abstract: A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/ 42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/.12% Mn/.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.

Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

Abstract: A process for manufacturing a multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.

Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.

Abstract: A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/0.12% Mn/0.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Abstract: A printed circuit board has a plurality of layers. A first surface land is formed on an inner layer. A dielectric material is laminated on the inner layer. A second surface land is formed on the dielectric material overlapping the inner surface land or positioned along the border of the inner surface land. A hole is etched in the dielectric material exposing the first surface land to the second surface land. The second surface land does not completely surround the hole. A component lead is positioned over the second surface land. Solder is reflowed into the hole to interconnect the surface lands to each other and to the component lead. Because the second surface land does not completely surround the hole, the solder does not bridge across the hole and thereby forms a solid connection between the first and second surface lands.

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract: A multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.

Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.

Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.