Abstract: A computer implemented method incrementally updates a design placement in a very large scale integrated (VLSI) chip. A data structure is generated which defines a chosen specification and initial placement of circuits is input to a computer aided design (CAD) system. The CAD system divides a design area into placement cells. Local constraint values and limits are computed and changes made in the design specification. Replacement regions are then identified, expanded, and replaced. Constraint values are recomputed and the steps of the method are repeated until no more changes are required.

Abstract: According to the present invention, a method of optimization by simulated annealing is provided that uses a spatial metric to localize the simulated annealing temperature, the move set, and the objects which the moves operate on. The method keeps a local history of the optimization process. The localization allows the simulated annealing process to adaptively control the annealing schedule of each local region independently. This allows the annealing temperature, move set, and the objects upon which the move set operates to each be adjusted for each region independently to maximize efficiency. This results in optimization of all regions in a quick and efficient manner.