Abstract: The present disclosure relates to a method for fabricating an array of nanoprojections, where the nanoprojections may include nanopillars, nanowires, nanoneedles or nanocones. The present disclosure also relates to an array of the nanoprojections, and to uses of such arrays.

Abstract: An exemplary method and system is disclosed that facilitate the integration of multiplexed single-cell impedance cytometry in a high throughput format, which can be deployed upstream from microfluidic sample preparation and/or downstream to microfluidic cell separation. In exemplary method and system may employ impedance-based quantification of cell electrophysiology on the same microfluidic chip (i.e., “on-chip”) to provide distinguishing phenotypic information on the sample, without the need for additional sample handling, preparation or dilution steps as would be needed for other flow cytometry techniques.

Abstract: An exemplary method and system is disclosed that facilitate the integration of multiplexed single-cell impedance cytometry in a high throughput format, which can be deployed upstream from microfluidic sample preparation and/or downstream to microfluidic cell separation. In exemplary method and system may employ impedance-based quantification of cell electrophysiology on the same microfluidic chip (i.e., “on-chip”) to provide distinguishing phenotypic information on the sample, without the need for additional sample handling, preparation or dilution steps as would be needed for other flow cytometry techniques.

Abstract: An exemplary method and system is disclosed that facilitate the integration of multiplexed single-cell impedance cytometry in a high throughput format, which can be deployed upstream from microfluidic sample preparation and/or downstream to microfluidic cell separation. In exemplary method and system may employ impedance-based quantification of cell electrophysiology on the same microfluidic chip (i.e., “on-chip”) to provide distinguishing phenotypic information on the sample, without the need for additional sample handling, preparation or dilution steps as would be needed for other flow cytometry techniques.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: Provided herein are methods of treating cancers characterized by a high expression of GFIIB, comprising administering a therapeutically effective amount of a KDMIA inhibitor.

Abstract: The packages described by this invention all have reduced “head space,” that is, the distance from lid to lens. Packages contain dimples to achieve this reduced head space. Specifically, packages are designed with dimple sag equal to or less than 1.90-mm, or volume displaced equal to or less than 360 ?l. Combined with the existing primary packaging, it has been found that such conditions provide for reduction in folded lens rate during shipping and handling. As well, lenses stored or having an extended time in low head space packages in a “foil down” orientation now have characteristics closer lenses stored in a “foil up orientation.” The packages finally include a foil 3D pattern at a smaller scale than the dimple, by embossing or other methods allowing reduce lens sticking to the foil as well as an added anti-counterfeiting measure.

Abstract: The packages described by this invention all have reduced “head space,” that is, the distance from lid to lens. Packages contain dimples to achieve this reduced head space. Specifically, packages are designed with dimple sag equal to or less than 1.90-mm, or volume displaced equal to or less than 360 ?l. Combined with the existing primary packaging, it has been found that such conditions provide for reduction in folded lens rate during shipping and handling. As well, lenses stored or having an extended time in low head space packages in a “foil down” orientation now have characteristics closer lenses stored in a “foil up orientation.” The packages finally include a foil 3D pattern at a smaller scale than the dimple, by embossing or other methods allowing reduce lens sticking to the foil as well as an added anti-counterfeiting measure.

Abstract: Systems and methods are provided for accessing and/or aggregating data from third party web sites. An aggregated candidate profile may be created and displayed based on information from a plurality of social networking profiles from various third party web sites. The social networking profiles may be identified based on automated analysis. The aggregated candidate may be created and/or displayed using a browser plug-in.

Abstract: Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.

Abstract: Method and apparatus for digital calibration of an analog-to-digital converter (ADC). One example relates to calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution. The A/D conversion system includes an ADC that generates an output having N most significant bits (MSBs) and M least significant bits (LSBs) (i.e., an N+M bit resolution). An offset calibration circuit is configured to determine an offset in the ADC and to compensate the N+M bit output using the offset to provide an N+M bit offset corrected output. A gain calibration circuit is configured to determine a gain correction factor for the ADC and to compensate the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

Abstract: Method and apparatus for an interface to a system monitor (1600) is described. A controller (102) accessible via a port interface thereof (110) is configured for read/write access to configuration memory cells (1500) and for read access to status registers (1602). The configuration memory cells (1500) are addressable via a first address space, and the status registers (1602) are addressable via a second address space different from the first address space. The port interface (110) is configured to receive a plurality of signals including a data address signal (124) and a data clock signal (121). The data address signal (124) has address information for accessing either the first address space or the second address space.

Abstract: Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.

Abstract: Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.

Abstract: Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.

Abstract: A subject (12) observes an image on a display (10). A control (18) produces a fixation image at a selected position in the display, followed by a stimulus spaced from the fixation image. An eye position sensor (14) detects a saccade movement towards the stimulus. The stimulus is then replaced with a fixation image and the cycle repeated. The time taken to saccade plus the intensity of the stimulus are used to produce a retinal map of field of vision, or to assess other characteristics of the subject.

Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.

Abstract: Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.