Patents by Inventor John McKenna Brennan

John McKenna Brennan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150025369
    Abstract: According to some embodiments a housing for the OCT comprises: (a) a tubular body with an inner diameter of less than 5 mm (for example less than 2 mm, and in some embodiments not greater than 1.5 mm), a first end, a second end; and a window formed in the tubular body closer to the second end than to the first end, displaced from the second end, and framed by a portion of the tubular body, wherein the window has a width w. According to some embodiments, 0.05 mm<w<8 mm.
    Type: Application
    Filed: June 24, 2014
    Publication date: January 22, 2015
    Inventors: Venkata Adiseshaiah Bhagavatula, John McKenna Brennan, Woraphat Dockchoorung, Klaus Hartkorn, Mark Alan McDermott, Amorn Runarom, Daniel Max Staloff
  • Publication number: 20130215924
    Abstract: According to one embodiment described herein, a method for assembling a multi-emitter laser pump package, includes providing a base substrate comprising a laser riser block. A chip-on-hybrid laser assembly is bonded to the laser riser block with a solder preform. A scalar module is bonded to the base substrate with an adhesive such that an output of the chip-on-hybrid laser assembly is optically coupled into an input of the scalar module. A sidewall ring is adhesively bonded to the base substrate with a non-hermetic adhesive, the sidewall ring comprising a fiber interconnect fitting and at least one electrical connector. A first end of a fiber interconnect is optically coupled to an output of the scalar module and a second end of the fiber interconnect is positioned in the fiber interconnect fitting of the sidewall ring.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 22, 2013
    Inventors: John McKenna Brennan, Wanchai Chinpongpan, Woraphat Dockchoorung, Sanyapong Puthgul, Amorn Runarom
  • Patent number: 7637414
    Abstract: An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: December 29, 2009
    Assignee: Agere Systems Inc.
    Inventors: Timothy Brooks Bambridge, John Wayne Bowen, John McKenna Brennan, Joseph Michael Freund
  • Publication number: 20080283578
    Abstract: An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.
    Type: Application
    Filed: July 11, 2008
    Publication date: November 20, 2008
    Applicant: Agere Systems Inc.
    Inventors: Timothy Brooks Bambridge, John Wayne Bowen, John McKenna Brennan, Joseph Michael Freund
  • Patent number: 7443042
    Abstract: An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 28, 2008
    Assignee: Agere Systems Inc.
    Inventors: Timothy Brooks Bambridge, John Wayne Bowen, John McKenna Brennan, Joseph Michael Freund
  • Patent number: 7164200
    Abstract: Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: January 16, 2007
    Assignee: Agere Systems Inc.
    Inventors: John McKenna Brennan, Joseph Michael Freund, John William Osenbach
  • Patent number: 7086148
    Abstract: An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: August 8, 2006
    Assignee: Agere Systems Inc.
    Inventors: Timothy Brooks Bambridge, John Wayne Bowen, John McKenna Brennan, Joseph Michael Freund
  • Patent number: 7075174
    Abstract: A method for attaching at least one IC die to a non-ceramic IC package including a leadframe and a base, the IC package being configured for receiving the at least one IC die, includes attaching the IC die to an upper surface of a thermal carrier in a manner which facilitates thermal transfer between the die and the carrier. The method further includes attaching the thermal carrier having the IC die attached thereto to an upper surface of the base of the IC package. In this manner, one or more IC dies may be attached to a standard plastic IC package without a significant impact on thermal transfer in the device and at a significant cost savings compared to ceramic IC packages.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: July 11, 2006
    Assignee: Agere Systems Inc.
    Inventors: John McKenna Brennan, Joseph Michael Freund, Curtis James Miller, Richard Handly Shanaman, III