Abstract: An apparatus including a buck circuitry and logic circuitry. The buck circuitry charges a flying capacitor with a voltage in response to a device state being in a charging state and discharges the voltage from the flying capacitor in response to the device state being in a discharging state. The logic circuitry causes the buck circuitry to transition the device state in response to detecting voltage balance during a reference time period and causes the buck circuitry to repeat the device state occurring at the reference time period in response to detecting voltage imbalance during the reference time period.

Abstract: A switching regulator including a buck controller and control logic. The buck controller compares a reference output voltage with an output voltage to obtain a control voltage. The control logic outputs pulses to the switches. The pulses sequence the transitioning of the switches. The control logic inhibits one or more of the pulses from transitioning in response to a voltage difference existing between the control voltage and the reference output voltage.

Abstract: A switching regulator including buck circuitry and an output voltage loop. The buck circuitry decreases a voltage level of an input voltage in response to converting the input voltage to an output voltage. The output voltage loop performs a digital-to-analog conversion on an output voltage setpoint to convert the output voltage setpoint from a digital word to a reference output voltage. The output voltage loop compares the reference output voltage with the output voltage to obtain a control voltage.

Abstract: An integrated circuit chip includes a vlimiter controller, a capacitive buck controller, a multi-level buck controller and a switch controller. The vlimiter controller outputs vlimiter signals that cause the integrated circuit chip to perform as a voltage limiter. The capacitive buck controller outputs capacitive buck signals that cause the integrated circuit chip to perform as a capacitive buck converter. The multi-level buck controller outputs multi-level buck signals that cause the integrated circuit chip to perform as a multi-level buck converter. The switch controller selects between the vlimiter signals, the capacitive buck signals and the multi-level buck signals.

Abstract: A power management unit accurately measures and controls charging current. The power management unit may be implemented more efficiently than prior designs, leading to cost savings in the implementation of the power management unit as well as in the implementation of the device that incorporates the power management unit. The power management unit incorporates a model of an external charge control device (e.g., a transistor) and uses that model in a way that allows the power management unit to eliminate external device pins and other circuitry.

Abstract: A power management unit accurately measures and controls charging current. The power management unit may be implemented more efficiently than prior designs, leading to cost savings in the implementation of the power management unit as well as in the implementation of the device that incorporates the power management unit. The power management unit incorporates a model of an external charge control device (e.g., a transistor) and uses that model in a way that allows the power management unit to eliminate external device pins and other circuitry.

Abstract: A power management unit accurately measures and controls charging current. The power management unit may be implemented more efficiently than prior designs, leading to cost savings in the implementation of the power management unit as well as in the implementation of the device that incorporates the power management unit. The power management unit incorporates a model of an external charge control device (e.g., a transistor) and uses that model in a way that allows the power management unit to eliminate external device pins and other circuitry.

Abstract: The highly efficient, high current drive, multi-phase voltage multiplier reduces the inefficiency due to the active level overlapping portion of the clock at high frequencies, reduces the inefficiency due to extremely large drive currents on the inverters supplying current to the multiplying capacitors C1(*) and C2(*), and increases the efficiency of the multiplier by allowing M-1 phases to charge the output at any given time and providing more time given to each capacitor to fully charge and discharge. The ripple on the output is much smaller than in a single dual phase multiplier. This multi-phase voltage multiplier supplies very large current to the load while remaining very efficient.

Abstract: A method and apparatus are provided for measuring high speed glitch energy between first and second. The method and apparatus induce a change in charge on the first node from a first charge level to a second charge level with glitch energy supplied by the second node. An amount of charge is then supplied to the first node to restore the charge on the first node from the second charge level toward the first charge level. A representation of the amount of charge supplied to the first node is measured.

Abstract: A termination impedance in a semiconductor circuit is trimmed to fall within a desired range by a trimming circuit such that the amount of variation in the termination impedance is less than the variation in the sheet rho (resistivity) of the semiconductor. An external reference resistor causes a reference current to flow in multiple branches of a current mirror circuit. One branch of the current mirror circuit has a resistance less than the reference resistor, another has a resistance approximately equal to the reference resistor, and another has resistance greater than the reference resistor. Variation in the sheet rho results voltage drops across the resistor in variation in the resistor values. A logic circuit detects the variations, and encodes a control signal. The control signal is received by a variable termination circuit that switches parallel resistance branches in or out of the termination impedance circuit such that an effective termination impedance is selected based upon the control signal.