Abstract: Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.