Patents by Inventor John Michael Hergenrother
John Michael Hergenrother has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8120138Abstract: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.Type: GrantFiled: May 6, 2009Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Patent number: 7696057Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: GrantFiled: January 2, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Patent number: 7687863Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.Type: GrantFiled: May 16, 2008Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
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Publication number: 20090212388Abstract: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.Type: ApplicationFiled: May 6, 2009Publication date: August 27, 2009Applicant: International Business Machines CorporationInventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Patent number: 7550361Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: GrantFiled: January 2, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Publication number: 20080217682Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.Type: ApplicationFiled: May 16, 2008Publication date: September 11, 2008Inventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
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Publication number: 20080157260Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Inventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Publication number: 20080157404Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Inventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Patent number: 7374998Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.Type: GrantFiled: February 3, 2006Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
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Patent number: 6903411Abstract: An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer.Type: GrantFiled: August 25, 2000Date of Patent: June 7, 2005Assignee: Agere Systems Inc.Inventors: Yih-Feng Chyan, John Michael Hergenrother, Donald Paul Monroe
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Patent number: 6828628Abstract: A diffused MOS device comprises one or more strained silicon portions formed in a carrier transit path of the DMOS device. The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path is at least partially defined by a body of the DMOS device, and may also include other regions, such as a diffusion area, channel region, or accumulation region. The one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed as a layer throughout. The one or more strained silicon portions may be formed through patterning of a hard mask, forming a lattice mismatch layer, forming a strained silicon layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.Type: GrantFiled: March 5, 2003Date of Patent: December 7, 2004Assignee: Agere Systems, Inc.Inventors: John Michael Hergenrother, Muhammed Ayman Shibib, Shuming Xu, Zhijian Xie
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Patent number: 6821851Abstract: A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material.Type: GrantFiled: August 27, 2003Date of Patent: November 23, 2004Assignee: Agere Systems Inc.Inventors: John Michael Hergenrother, Pranav Kalavade
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Publication number: 20040173846Abstract: A diffused MOS device comprises one or more strained silicon portions formed in a carrier transit path of the DMOS device. The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path is al least partially defined by a body of the DMOS device, and may also include other regions, such as a diffusion area, channel region, or accumulation region. The one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed as a layer throughout. The one or more strained silicon portions may be formed through patterning of a hard mask, forming a lattice mismatch layer, forming a strained silicon layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.Type: ApplicationFiled: March 5, 2003Publication date: September 9, 2004Inventors: John Michael Hergenrother, Muhammed Ayman Shibib, Shuming Xu, Zhijian Xie
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Publication number: 20040152269Abstract: A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material.Type: ApplicationFiled: August 27, 2003Publication date: August 5, 2004Inventors: John Michael Hergenrother, Pranav Kalavade
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Patent number: 6653181Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.Type: GrantFiled: August 2, 2002Date of Patent: November 25, 2003Assignee: Agere Systems Inc.Inventors: John Michael Hergenrother, Donald Paul Monroe
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Patent number: 6635924Abstract: A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material.Type: GrantFiled: June 6, 2002Date of Patent: October 21, 2003Assignee: Agere Systems Inc.Inventors: John Michael Hergenrother, Pranav Kalavade
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Publication number: 20030057477Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices.Type: ApplicationFiled: August 2, 2002Publication date: March 27, 2003Inventors: John Michael Hergenrother, Donald Paul Monroe
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Patent number: 6197641Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers.Type: GrantFiled: June 18, 1999Date of Patent: March 6, 2001Assignee: Lucent Technologies Inc.Inventors: John Michael Hergenrother, Donald Paul Monroe, Gary Robert Weber