Patents by Inventor John N. M. Peirce

John N. M. Peirce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030199153
    Abstract: Disclosed is a method of producing elementary semiconductor devices such as a field-effect transistor, a capacitor, a resistor, an inductor, a transformer, or a diode, and devices produced by said method. According to the method, a semiconductor seed layer is applied to a substrate having regions of exposed semiconductor material and regions of exposed dielectric material. The method comprises a step of disposing the substrate in a growth chamber and nucleating the seed layer by exposing the semiconductor material and dielectric material to an atmosphere of gases presented at a predetermined flow rate, temperature and pressure selected to provide contiguous growth of the seed layer, the seed layer growing in a single crystal lattice over predetermined windows within the mixed topology substrate.
    Type: Application
    Filed: December 23, 2002
    Publication date: October 23, 2003
    Inventors: Stephen J. Kovacic, John N.M. Peirce, John William Mitchell Rogers, Nader Fayyaz, David Rahn
  • Publication number: 20030107426
    Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen the a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.
    Type: Application
    Filed: March 14, 2002
    Publication date: June 12, 2003
    Inventors: Navid Foroudi, John N.M. Peirce
  • Patent number: 6433611
    Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: August 13, 2002
    Assignee: SiGe Microsystems Inc.
    Inventors: Navid Foroudi, John N. M. Peirce