Patents by Inventor John N. Randall

John N. Randall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7799132
    Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: September 21, 2010
    Assignee: Zyvex Labs, LLC
    Inventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, Robert J. Folaron
  • Patent number: 7326293
    Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 5, 2008
    Assignee: Zyvex Labs, LLC
    Inventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, II, Robert J. Folaron
  • Patent number: 7094292
    Abstract: A mechanism and method for depositing oil paints, acrylics, or other textural paints provides a means for automating the process of painting a picture. The process can be programmed into a data base which is stored and used at will, or the artist can utilize control means such as a joy stick to provide real-time input.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: August 22, 2006
    Inventors: John N. Randall, Christian H. Seidler, Charles D. Gray, Jr.
  • Patent number: 6837723
    Abstract: A deflection element operating under control of selectively applied energy is used to achieve low insertion loss between mating elements. Once the elements are in proper relationship the deflection element is allowed to settle to its stable position thereby serving to lock the elements together.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: January 4, 2005
    Assignee: Zyvex Corporation
    Inventors: John N. Randall, Matthew D. Ellis
  • Patent number: 6813378
    Abstract: A design tool which accepts the input of a grayscale underpainting and a number of artistic selections, such as primary colors, levels of intensity for each color, and lines of color drawn on a copy of the grayscale underpainting and forms a data base which can be used by a painting tool to create a Matrix painting.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: November 2, 2004
    Inventors: John N. Randall, Christian H. Seidler
  • Publication number: 20040099891
    Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.
    Type: Application
    Filed: November 20, 2003
    Publication date: May 27, 2004
    Inventors: Manoj Mehrotra, John N. Randall, Mark S. Rodder
  • Patent number: 6686102
    Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: John N. Randall, Gene E. Fuller
  • Patent number: 6686300
    Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, John N. Randall, Mark S. Rodder
  • Patent number: 6634018
    Abstract: An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: October 14, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: John N. Randall, Thomas J. Aton, Shane R. Palmer
  • Publication number: 20030077526
    Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).
    Type: Application
    Filed: November 27, 2002
    Publication date: April 24, 2003
    Inventors: John N. Randall, Gene E. Fuller
  • Patent number: 6553558
    Abstract: A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Shane R. Palmer, John N. Randall, Thomas J. Aton
  • Publication number: 20020113277
    Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.
    Type: Application
    Filed: October 25, 2001
    Publication date: August 22, 2002
    Inventors: Manoj Mehrotra, John N. Randall, Mark S. Rodder
  • Publication number: 20020094492
    Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr;, that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Inventors: John N. Randall, Gene E. Fuller
  • Publication number: 20020078427
    Abstract: A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 20, 2002
    Inventors: Shane R. Palmer, John N. Randall, Thomas J. Aton
  • Publication number: 20020026626
    Abstract: An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 28, 2002
    Inventors: John N. Randall, Thomas J. Aton, Shane R. Palmer
  • Publication number: 20020007580
    Abstract: A shotgun having identification grooves within at least part of the barrel, in a unique pattern which corresponds to the a recorded serial number of the shotgun (or of the barrel). The grooves are dimensioned to mark the polymer wadding which is normally included in a shotshell. The ejected wadding is thereby marked with identification data which can be used later to identify the gun.
    Type: Application
    Filed: February 28, 2001
    Publication date: January 24, 2002
    Inventors: John N. Randall, Patrice M.S. Randall
  • Publication number: 20020005868
    Abstract: A design tool which accepts the input of a grayscale underpainting and a number of artistic selections, such as primary colors, levels of intensity for each color, and lines of color drawn on a copy of said grayscale underpainting and forms a data base which can be used by a painting tool to create a Matrix painting.
    Type: Application
    Filed: April 18, 2001
    Publication date: January 17, 2002
    Inventors: John N. Randall, Christian H. Seidler
  • Publication number: 20020000973
    Abstract: A mechanism and method for depositing oil paints, acrylics, or other textural paints provides a means for automating the process of painting a picture. The process can be programmed into a data base which is stored and used at will, or the artist can utilize control means such as a joy stick to provide real-time input.
    Type: Application
    Filed: April 18, 2001
    Publication date: January 3, 2002
    Inventors: John N. Randall, Christian H. Seidler, Charles D. Gray
  • Publication number: 20010029690
    Abstract: In a rifle or handgun, identification grooves, which are shallower than the rifling grooves, are formed in a pattern unique to a particular gun, providing a means of identifying the gun through which a bullet was shot. This identification can be used by forensic labs to tie a fired bullet to a gun having a particular serial number, even if the gun is not available for examination. The data mechanically encoded preferably include redundant bits which provide error control coding, thereby making identification both easier and more certain. The pattern is preferably formed by a mechanically-invariant process (such as EDM or photoengraving).
    Type: Application
    Filed: February 28, 2001
    Publication date: October 18, 2001
    Inventors: Patrice M.S. Randall, John N. Randall
  • Publication number: 20010027619
    Abstract: A firearm in which a mechanical identification is integral with the surface of the chamber. Preferably the identification markings are elongated (ridges or grooves) in the direction of spent casing extraction. The extracted casings are thereby marked with a unique weapon identification number, which can easily be read by standard forensics methods.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 11, 2001
    Inventors: John N. Randall, Patrice M. S. Randall