Abstract: A sound damping wallboard and methods of forming a sound damping wallboard are disclosed. The sound damping wallboard comprises a gypsum layer with a gypsum surface having an encasing layer. The encasing layer is partially removed to expose the gypsum surface and form a gypsum surface portion and a first encasing layer portion on the gypsum layer. A sound damping layer is applied to the gypsum layer to cover at least part of the gypsum surface portion and the encasing layer portion.

Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.

Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.

Abstract: A mechanism and method for depositing oil paints, acrylics, or other textural paints provides a means for automating the process of painting a picture. The process can be programmed into a data base which is stored and used at will, or the artist can utilize control means such as a joy stick to provide real-time input.

Abstract: A deflection element operating under control of selectively applied energy is used to achieve low insertion loss between mating elements. Once the elements are in proper relationship the deflection element is allowed to settle to its stable position thereby serving to lock the elements together.

Abstract: A design tool which accepts the input of a grayscale underpainting and a number of artistic selections, such as primary colors, levels of intensity for each color, and lines of color drawn on a copy of the grayscale underpainting and forms a data base which can be used by a painting tool to create a Matrix painting.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.

Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).

Abstract: A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr;, that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).

Abstract: A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.

Abstract: An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.

Abstract: A shotgun having identification grooves within at least part of the barrel, in a unique pattern which corresponds to the a recorded serial number of the shotgun (or of the barrel). The grooves are dimensioned to mark the polymer wadding which is normally included in a shotshell. The ejected wadding is thereby marked with identification data which can be used later to identify the gun.

Abstract: A design tool which accepts the input of a grayscale underpainting and a number of artistic selections, such as primary colors, levels of intensity for each color, and lines of color drawn on a copy of said grayscale underpainting and forms a data base which can be used by a painting tool to create a Matrix painting.

Abstract: A mechanism and method for depositing oil paints, acrylics, or other textural paints provides a means for automating the process of painting a picture. The process can be programmed into a data base which is stored and used at will, or the artist can utilize control means such as a joy stick to provide real-time input.

Abstract: In a rifle or handgun, identification grooves, which are shallower than the rifling grooves, are formed in a pattern unique to a particular gun, providing a means of identifying the gun through which a bullet was shot. This identification can be used by forensic labs to tie a fired bullet to a gun having a particular serial number, even if the gun is not available for examination. The data mechanically encoded preferably include redundant bits which provide error control coding, thereby making identification both easier and more certain. The pattern is preferably formed by a mechanically-invariant process (such as EDM or photoengraving).