Patents by Inventor John Neilson

John Neilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6274892
    Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: August 14, 2001
    Assignee: Intersil Americas Inc.
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
  • Patent number: 6194290
    Abstract: A method for making at least one semiconductor power device with current conduction in a vertical direction from a plurality of semiconductor substrates includes processing at least one surface of each of two semiconductor substrates to form at least one of a metal layer and a doped region. The substrates are bonded together so that the at least one processed surface of each of the two semiconductor substrates define outer surfaces of the semiconductor device. The method further includes annealing the bonded together substrates at an anneal temperature so as to not adversely effect the processed surfaces. The method allows the making of a double sided semiconductor power device with a reduction in the number of sequential processing steps. The direct bonding approach allows current production recipes for fabricating single sided power devices to be used without requiring a separate process sequence.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: February 27, 2001
    Assignee: Intersil Corporation
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
  • Patent number: 6153495
    Abstract: A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200 .mu.m. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer. An implanted region may be formed at a surface of the at least one substrate opposite the processed surface prior to bonding.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: November 28, 2000
    Assignee: Intersil Corporation
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson