Abstract: One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Abstract: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Abstract: Embodiments of memory modules and corresponding methods are disclosed. One memory module embodiment includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Abstract: In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: The length of the phase lock feedback path of the phase lock loop chip (PLL chip) is adjusted so that the timing of clock pulses at computer chips is measured relative to the arrival time of a clock pulse at the computer board clock pin. This adjustment of the length of the phase lock loop accounts for the length of the trace from the computer board clock pin to the PLL clock input pin. This adjustment of the length of the phase lock loop removes uncertainty between vendors in the arrival time of clock pulses at the computer chips, relative to arrival time of clock pulses at the computer board clock pin. A system designer then has control of the arrival time of a pulse at a computer chip clock pin by adjustment of the arrival time of the clock pulse at the computer board clock pin, and no variation is introduced between vendors who adopt the invention in their design of computer boards.

Abstract: Printed Circuit Board fabrication costs are decreased, and device placement densities are increased by the use of well structures designed for receiving components such as capacitors on portions of the PCB directly beneath integrated circuit packages having very low vertical profiles. With such an arrangement it is possible to use newer low profile packages and still place a capacitor under the integrated circuit package for reduced area consumption and improved inductance and circuit cycle times. Further advantages of the present arrangement include a reduction in the number of vias that need to be drilled in the PCB to make capacitor attachments, a consequent improvement in PCB inductance and parasitic capacitance, and improved electrical properties for voltage reference planes and routing layers.