Patents by Inventor John Newlin

John Newlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9164922
    Abstract: An example method for passive compaction of a cache includes determining first metadata associated with first data and second metadata associated with second data. The first metadata includes a first retrieval time, and the second metadata includes a second retrieval time. The example method further includes obtaining a first metadata key including a first unique identifier and obtaining a second metadata key including a second unique identifier. The example method also includes generating a first data key and generating a second data key. The example method further includes writing, at a client device, the first and second data to the cache. Each of the first and second data occupy one or more contiguous blocks of physical memory in the cache, and the first and second data are stored in the cache in an order based on the relative values of the first and second retrieval times.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 20, 2015
    Assignee: Google Inc.
    Inventors: John Newlin, Jeffrey Adgate Dean
  • Publication number: 20150169470
    Abstract: An example method for passive compaction of a cache includes determining first metadata associated with first data and second metadata associated with second data. The first metadata includes a first retrieval time, and the second metadata includes a second retrieval time. The example method further includes obtaining a first metadata key including a first unique identifier and obtaining a second metadata key including a second unique identifier. The example method also includes generating a first data key and generating a second data key. The example method further includes writing, at a client device, the first and second data to the cache. Each of the first and second data occupy one or more contiguous blocks of physical memory in the cache, and the first and second data are stored in the cache in an order based on the relative values of the first and second retrieval times.
    Type: Application
    Filed: July 11, 2012
    Publication date: June 18, 2015
    Applicant: Google Inc.
    Inventors: John Newlin, Jeffrey Adgate Dean
  • Patent number: 8818092
    Abstract: Methods, systems and computer-readable storage mediums encoded with computer programs executed by one or more processors for rendering text within an image are disclosed. A block of text is segmented into a plurality of text segments, wherein each text segment comprises a sequence of characters. On each of a plurality of threads running in parallel, a text bitmap is generated for a respective text segment from the plurality of text segments, the text bitmap illustrating the sequence of characters for the respective text segment. Each of the text bitmaps are composited with an image bitmap of a source image, wherein the composited image bitmap comprises a rendering of the block of text onto the source image.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Google, Inc.
    Inventor: John Newlin
  • Patent number: 7080283
    Abstract: A system for providing simultaneous, real-time trace and debug of a multiple processing core system on a chip (SoC) is described. Coupled to each processing core is a debug output bus. Each debug output bus passes a processing core's operation to trace capture nodes connected together in daisy-chains. Trace capture node daisy-chains terminate at the trace control module. The trace control module receives and filters processing core trace data and decides whether to store processing core trace data into trace memory. The trace control module also contains a shadow register for capturing the internal state of a traced processing core just prior its tracing. Stored trace data, along with the corresponding shadow register contents, are transferred out of the trace control module and off the SoC into a host agent and system running debugger hardware and software via a JTAG interface.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 18, 2006
    Assignee: Tensilica, Inc.
    Inventors: Christopher M. Songer, John Newlin, Srikanth Nuggehalli, David Glen Jacobowitz
  • Patent number: 6986127
    Abstract: A debugging system and debugging techniques for configurable processors remove the requirement of foreknowledge of specific configurable processor information from components of the debugging system where obtaining that foreknowledge is costly. The system is part of an environment that generates a processor where the proper information is generated in the right forms for such use.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: January 10, 2006
    Assignee: Tensilica, Inc.
    Inventors: John Newlin, Albert Wang, Christopher M. Songer