Patents by Inventor John Nicholas Wilson
John Nicholas Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120250777Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: April 9, 2012Publication date: October 4, 2012Applicant: Sony Europe LimitedInventors: Jean-Luc PERON, Matthew Paul Athol TAYLOR, Samuel Asanbeng ATUNGSIRI, John Nicholas WILSON
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Publication number: 20120212665Abstract: A receiver comprises a first signal acquisition unit for acquiring a first type of signal block formatted according to a first format, the first signal acquisition unit comprising one or more parameter estimation units for estimating from the received signals one or more signal parameters related to acquisition of the first type of signal block, and wherein where the first type of signal block is interleaved with a second type of signal block formatted according to a second format, one or more parameter estimation units are arranged in operation to conduct signal parameter estimation based upon one or more respective properties of the received second type of signal block prior to continuation of the estimation based upon one or more respective properties of the received first type of signal block.Type: ApplicationFiled: November 25, 2011Publication date: August 23, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol TAYLOR, John Nicholas Wilson
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Patent number: 8208525Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: October 24, 2008Date of Patent: June 26, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8208524Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i-1[0]?R?i-1[2], and the permutation code forms, with an additional bit, a twelve bit address.Type: GrantFiled: October 23, 2008Date of Patent: June 26, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20120147981Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of Ri?[10]=Ri-1?[0]?Ri-1?[2], and the permutation code forms, with an additional bit, a twelve bit address.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol TAYLOR, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8199802Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: October 22, 2008Date of Patent: June 12, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20120134431Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: February 1, 2012Publication date: May 31, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol TAYLOR, Samuel Asanbeng ATUNGSIRI, John Nicholas WILSON
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Publication number: 20120127372Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: SONY CORPORATIONInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8179954Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.Type: GrantFiled: October 10, 2008Date of Patent: May 15, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asangbeng Atungsiri, John Nicholas Wilson
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Publication number: 20120106673Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asangbeng Atungsiri, John Nicholas Wilson
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Patent number: 8170091Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: October 23, 2008Date of Patent: May 1, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20120099665Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: December 30, 2011Publication date: April 26, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Patent number: 8155178Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: GrantFiled: October 10, 2008Date of Patent: April 10, 2012Assignee: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20120069922Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: November 21, 2011Publication date: March 22, 2012Applicant: Sony CorporationInventors: Matthew Paul Athol TAYLOR, Samuel Asanbeng ATUNGSIRI, John Nicholas WILSON
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Publication number: 20100296593Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: October 24, 2008Publication date: November 25, 2010Applicant: SONY CORPORATIONInventors: Samuel Asanbeng Atungsiri, Matthew Paul Athol Taylor, John Nicholas Wilson
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Publication number: 20090110093Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.Type: ApplicationFiled: October 10, 2008Publication date: April 30, 2009Applicant: SONY CORPORATIONInventors: Matthew Paul Athol TAYLOR, Samuel Asanbeng ATUNGSIRI, John Nicholas WILSON
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Publication number: 20090110097Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i?1[0]?R?i?1[2], and the permutation code forms, with an additional bit, a twelve bit address.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20090110095Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is R?i[8]=R?i?1[0]?R?i?1[4], and a permutation code is provided for permuting the order of the content of the register stages.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20090110094Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R?i[11]=R?i-1[0]R?i-1[1]R?i-1[4]R?i-1[6], and the permutation code forms, with an additional bit, a thirteen bit address.Type: ApplicationFiled: October 22, 2008Publication date: April 30, 2009Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson
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Publication number: 20090110098Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has ten register stages with a generator polynomial for the linear feedback shift register of R?i[9]=R?i?1[0] ?R?i?1[3], and the permutation code forms, with an additional bit, an eleven bit address.Type: ApplicationFiled: October 24, 2008Publication date: April 30, 2009Applicant: Sony CorporationInventors: Matthew Paul Athol Taylor, Samuel Asanbeng Atungsiri, John Nicholas Wilson