Patents by Inventor John Niven

John Niven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607983
    Abstract: A system for discretely packaging liquid or solid medication, or other substances, comprising a tray (10) with individual compartments (12) each containing a removable pot (17) and a perforated sealed sheet (21) enabling individual pots to be removed from the tray (10) for dispensing of its contents. The system also includes a computer and printer with software to create printed matter for the sheet (21) representative of the contents of the individual pots (17). An outer container (24) may receive several such filled and sealed trays (10) and an information sheet (28). One or more windows (30) in the container (24) provide a visual display of the contents. The system enables safe, accurate and easy packaging and dispensing of medication or other substances.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 17, 2013
    Assignee: Protomed Limited
    Inventors: Norman Niven, John Niven
  • Publication number: 20100236960
    Abstract: A system for discretely packaging liquid or solid medication, or other substances, comprising a tray (10) with individual compartments (12) each containing a removable pot (17) and a perforated sealed sheet (21) enabling individual pots to be removed from the tray (10) for dispensing of its contents. The system also includes a computer and printer with software to create printed matter for the sheet (21) representative of the contents of the individual pots (17). An outer container (24) may receive several such filled and sealed trays (10) and an information sheet (28). One or more windows (30) in the container (24) provide a visual display of the contents. The system enables safe, accurate and easy packaging and dispensing of medication or other substances.
    Type: Application
    Filed: October 8, 2008
    Publication date: September 23, 2010
    Inventors: Norman Niven, John Niven
  • Publication number: 20080024152
    Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage reduces leakage current associated with the devices under test. Accordingly, heat dissipation is reduced during burn-in.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 31, 2008
    Inventors: Eric Sheng, David Hoffman, John Niven
  • Publication number: 20070271061
    Abstract: Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 22, 2007
    Inventors: Eric Sheng, David Hoffman, John Niven
  • Publication number: 20050192773
    Abstract: Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 1, 2005
    Inventors: Eric Sheng, David Hoffman, John Niven
  • Patent number: 6850075
    Abstract: An integrated circuit includes a test circuit that may be configured to generate a test signal having a predetermined pulse width in response to a control input. The test signal may track process corners of the integrated circuit and may be used to predict a failure of the integrated circuit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 1, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Colin Davidson, John Niven