Abstract: A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an accessed one of the controller circuits and one of a plurality of first busses. The arbiter circuit may be configured to control access to the controller circuits by the line buffer circuits.

Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Abstract: A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.

Abstract: A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.