Abstract: Method of infusing or introducing material into a substrate using a gas cluster ion beam. The method includes maintaining a reduced-pressure environment around a substrate holder and holding a substrate securely within that reduced-pressure environment. A gas-cluster ion beam formed from a pressurized gas mixture including an inert gas and at least one other atomic or molecular specie is provided to the reduced-pressure environment and accelerated. In one embodiment, the method includes irradiating the accelerated gas-cluster ion beam onto one or more surface portions of the substrate to form an infused region or gas-cluster ion-impact region therein by introducing part or all of the atomic or molecular specie into the surface. In another embodiment, the method includes modifying at least one electrical property of the surface of the substrate by irradiating the accelerated gas-cluster ion beam onto one or more surface portions of the substrate.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: Methods and apparatus are described for irradiating one or more substrate surfaces with accelerated gas clusters including strain-inducing atoms for blanket and/or localized introduction of such atoms into semiconductor substrates, with additional, optional introduction of dopant atoms and/or C. Processes for forming semiconductor films infused into and/or deposited onto the surfaces of semiconductor and/or dielectric substrates are also described. Such films may be doped and/or strained as well.

Abstract: Methods are provided for fabrication of a circuit on a substrate. After formation of gate electrodes, sidewall spacers are formed on the sides of the gate electrodes. Source/drain extensions and source/drain regions of p-type devices are implanted through openings in a first mask. Source/drain extensions and source/drain regions of n-type devices are implanted through openings in a second mask. The source/drain extensions are implanted at low energy and at a high tilt angle with respect to a normal to the substrate surface, so that the source/drain extensions are formed laterally under the sidewall spacers. The source/drain regions are implanted at low or zero tilt angle and at equal to or higher energy and higher dose than the steps of implanting the source/drain extensions. In one optional feature, the first and second masks are used for implanting wells, channel stops and threshold adjusts for the p-type devices and the n-type devices, respectively.

Abstract: CMOS vertically modulated wells are constructed by using a blanket implant to form a blanket buried layer and then using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation in addition to said blanket buried layer.

Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: CMOS vertically modulated wells are constructed by using clustered MeV ion implantation to form a structure having a buried implanted layer for laterial isolation.