Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: The present invention relates to a method of treating disorders of the Central Nervous System (CNS) and other disorders in a mammal, including a human, by administering to the mammal a CNS-penetrant &agr;7 nicotinic receptor agonist. It also relates to pharmaceutical compositions containing a pharmaceutically acceptable carrier and a CNS-penetrant &agr;7 nicotinic receptor agonist.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.

Abstract: An apparatus and method for facilitating an anonymous shipment, including a memory device for storing information regarding the identity and shipping address for at least one individual, a receiver for receiving an order for at least one of a good and a service, a processor for processing the order for the at least one of a good and a service, wherein the processor generates an order message, wherein the order message contains a shipping message containing at least one of an anonymous shipping address information, an encoded shipping address information, an encrypted shipping address information, and a disguised shipping address information, wherein the shipping message conceals the address of an individual who at least one of placed the order and is to receive the shipment, and a transmitter for transmitting the order message to a provider of at least one of goods and services for order fulfillment.

Abstract: A method for etching at least partially through a transition metal-containing layer disposed above a substrate is disclosed. The transition metal-containing layer is disposed below an etch mask. The method includes providing a plasma processing system having a plasma processing chamber, and configuring the plasma processing chamber to etch the transition metal-containing layer. The plasma processing chamber configuring process includes configuring the plasma processing chamber to receive a source gas that includes HCl and Ar, and configuring a power supply associated with the plasma processing chamber to supply energy to strike a plasma from the source gas. The plasma processing chamber configuring process further includes configuring the plasma processing chamber to etch at least partially the transition metal-containing layer with the plasma.

Abstract: A method is provided for securing a wellbore tool assembly to a wellbore tubular member, which includes a number of method steps. The wellbore tubular member is provided, and defines a surface with a substantially cylindrical shape having a selected tubular diameter. A wellbore tool assembly is likewise provided, and includes a plurality of ring-shaped components, with at least one ring-shaped component defining a cylindrical surface having a selected ring diameter which differs from the tubular diameter of the wellbore tubular member. A plurality of radial groove members and radial land members are formed on at least one of the cylindrical surface of the wellbore tubular member and the cylindrical surface of the at least one ring-shaped component of the wellbore tool assembly. The wellbore tubular member and the at least one ring-shaped component of the wellbore tool assembly are urged to differing thermal conditions to cause the tubular diameter and the ring diameter to become substantially equal.

Abstract: A method is provided for securing a wellbore tool assembly to a wellbore tubular member, which includes a number of method steps. The wellbore tubular member is provided, and defines a surface with a substantially cylindrical shape having a selected tubular diameter. A wellbore tool assembly is likewise provided, and includes a plurality of ring-shaped components, with at least one ring-shaped component defining a cylindrical surface having a selected ring diameter which differs from the tubular diameter of the wellbore tubular member. A plurality of radial groove members and radial land members are formed on at least one of the cylindrical surface of the wellbore tubular member and the cylindrical surface of the at least one ring-shaped component of the wellbore tool assembly. The wellbore tubular member and the at least one ring-shaped component of the wellbore tool assembly are urged to differing thermal conditions to cause the tubular diameter and the ring diameter to become substantially equal.

Abstract: A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications.

Abstract: A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

Abstract: A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

Abstract: The present invention relates to signal coding, and particularly, though not exclusively, to coding of video signals, especially using conditional replenishment coding, where information is transmitted only in respect of elements of a frame of the picture which have changed relative to the previous frame; the transmitted data being used at a receiver to update a stored version of the picture. According to one aspect of the present invention there is provided a method of coding a set of values comprising selecting that one of a plurality of possible sequences of the values which has the highest correlation between successive values in the sequence, and supplying representations of those values to an output; wherein some of the representations are the differences between the relevant value and a prediction based on at least the immediately preceding value in the selected sequence. Although the method is applicable to other forms of signal, it finds particular application in video coding.

Abstract: A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

Abstract: In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.