Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does not possess the token, then the device may not use the analog signal. In another implementation, the controller may transmit a peer-to-peer message to a selected device. When the selected device receives the peer-to-peer message, then the selected device may use the analog signal. In this manner, the controller ensures that only one device at a time may use the analog signal.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: Systems and methods are disclosed for generating and displaying a POI data associated with multiple searches on a single digital map. Searches may be activated from pre-set layers within a layer panel. Searches may also be activated by adding custom layers.

Abstract: Systems and methods are disclosed for generating and displaying a POI data associated with multiple searches on a single digital map. Searches may be activated from pre-set layers within a layer panel. Searches may also be activated by adding custom layers.

Abstract: Systems and methods are disclosed for generating and displaying a POI data associated with multiple searches on a single digital map. Searches may be activated from pre-set layers within a layer panel. Searches may also be activated by adding custom layers.

Abstract: A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.

Abstract: A single face splicer for creating a splice between a running web from a first source of single face material and a ready web from a second source of single face material to provide an uninterrupted supply of single face material to a double backer system in the manufacture of corrugated cardboard. The splicer includes an upper and lower bridge positioned above the first and second sources of single face material, and a splice head adjacent the upper bridge for creating the splice between the running web and the ready web. A drive system draws the running web through the splice head at an output speed which is greater than the speed at which the double backer system draws the running web from the splicer. The running web is deposited on an upper bridge supply belt which rotates at a speed which is slower than the output speed thereby causing the running web to accumulate on the upper bridge supply belt.

Abstract: An input festoon is provided in a web supply apparatus for automatically splicing a relatively stiff web of material such a liner board for making corrugated board. The input festoon includes a dancer roll which is movable along a track to allow storage of a ready web as the ready web is pre-accelerated by an accelerator roll to a running speed prior to creation of a splice at a splice head. Tail grab sensors are mounted on the apparatus above the web between the input roll and the splice head adjacent the input roll. The tail grab sensor detects tears or breaks in the web and provides an electrical signal to initiate a splice. A vacuum box including a pivotable vacuum bar is provided for creating a high speed butt splice. A method of creating a high speed butt splice using the vacuum box is also presented.