Abstract: A receiver for use in receipt of signals on railroad rails which converts the rail signal to a higher frequency and feeds the higher frequency signal into an input transformer. The secondary of the input transformer is in a tuned circuit which is resonate at the higher frequency and which contains a winding of an output transformer. The tuned circuit can be tuned to the higher frequency by series components such as a resistor and capacitor.

Abstract: The circuit arrangement of this invention includes a signal searchlight wherein the lamp is in an electrical series circuit with interlock contact switches. The switches interlock the display color lens such as yellow and green to control the electrical energization of the signal circuit. Logic control switching devices in a remote wayside control box supply signals through a cable to operate a bipolar device to selectively display the desired color.

Abstract: An electronic bipolar interface driver circuit for interconnecting a microprocessor to an electromagnetic relay load. The driver circuit includes a peripheral adapter circuit having a pair of outputs connected to a respective one of the two inputs of a pair of NAND gates. A source of square-wave signals connected to the other inputs of the two input NAND gates so that a.c. signals are supplied to one of two switching amplifiers. The a.c. signals are transformer-coupled to a pair of rectifiers. The rectified d.c. voltage is supplied to either one of two switching transistors which establishes a given polarity of voltage on a pair of output terminals and which illuminates one of two optical couplers to feedback a checking signal to the peripheral adapter circuit to verify the polarity of the voltage on the output terminals.

Abstract: A vital checking circuit for assuring the reception of only one input signal including a differential amplifier having a pair of PNP transistors. A voltage divider having a first and a second biasing resistor connected to the input of one of the pair of transistors. An a.c. signal transformer coupled to the input of the one of the pair of transistors. A third biasing resistor connected to the input of the other of the pair of transistors. A plurality of current-drawing circuits connected to the third biasing resistor, and an a.c. output signal derived from the other of the pair of transistors when and only when one of the plurality of current-drawing circuits is drawing current through the third biasing resistor.

Abstract: A vital low frequency code generating circuit having a pair of complementary unijunction transistor relaxation oscillators for producing coincidental pulses in the absence of any failure; and a first initially nonconductive transistor amplifier and a second initially conductive transistor amplifier for saturating a square loop core transformer in a positive direction. The coincidental pulses causing the first transistor amplifier to be rendered nonconductive to unsaturate the square loop core transformer and causing the second transistor amplifier to be rendered conductive to saturate the square loop core transformer in the negative direction, which results in the development of output code pulses only when neither of the relaxation oscillators has drifted appreciably.

Abstract: A separate relay is connected across the output of each speed command filter decoder in the train carried apparatus, except that decoder associated with the highest authorized speed. Each relay has special make-and-break contacts which cannot be simultaneously closed in normal operation. When the relay is energized by an output from the associated decoder, the normally open contacts close to apply that speed command to the corresponding input of the speed governor. The associated normally closed contacts open at the same time to remove operating energy from all higher speed decoders to inhibit simultaneous response from any cause. This action assures that the train is controlled by the lowest active speed command if more than one filter decoder inadvertently responds to produce simultaneous speed command outputs.

Abstract: The speed proportional frequency signal from the speed generator being checked is amplified and applied to a highpass filter-rectifier with a low frequency limit corresponding to a predetermined minimum train speed. Polarity of the rectified output is opposite to the DC operating energy so that, with four-terminal load resistor and smoothing capacitor, the filter-rectifier operation is vital. The rectified signal activates an oscillator level detector when its level exceeds the breakdown of a Zener diode control device selected to correspond to minimum speed output. The level detector is coupled by a stepdown transformer to a differential amplifier biased by a signal supplied from an associated zero speed detector. The bias signal has sufficient level to enable the differential amplifier to produce an output in response to the level detector input only when the train speed is greater than zero.

Abstract: A fail-safe active low-pass filter circuit including a plurality of transistor gates having their inputs coupled to a source of a.c. signals, one of a plurality of field-effect transistor switches coupled to an associated one of the plurality of transistor gates, and a variable R-C network having a variable upper a.c. signal passing level which is determined by which one of the associated transistor gates and field-effect switches is rendered conductive by application of d.c. supply voltage.

Abstract: A transistorized power supply for providing a constant voltage to a load. A series regulator interposed between a d.c. input voltage source and the load to regulate the d.c. output voltage. A d.c. to d.c. converter serially connected between the d.c. input voltage source and the series regulator. The d.c. to d.c. converter is selectively actuated to supplement the d.c. input voltage when the d.c. input voltage falls below a predetermined value in order to maintain a constant voltage across the load.

Abstract: An electronic cab signal test set employing an integrated circuit code oscillator for producing a code signal and an integrated circuit carrier oscillator for producing a carrier signal which is modulated by the code signal to produce a code carrier signal. The coded carrier signal drives a current source which injects current signals directly into a pair of series aiding pickup coils for testing the integrity of the pickup coils and for checking the sensitivity of the amplifier. An indicating circuit including a voltage sensing device, a switching circuit, and an illuminating device connected to the code carrier for evaluating the condition of the d.c. supply source and for indicating that the test set is properly functioning.

Abstract: A self-powered receiver including a series resonant circuit tuned to the carrier frequency of a modulated carrier signal. A demodulator for detecting the envelope which switches a switching transistor ON during the mark portions of the modulator carrier signals and switches the switching transistor OFF during the space portions. A parallel resonant circuit is driven by the switching transistor to produce a.c. modulations to be coupled to a full-wave rectifier. The rectified voltage of the rectifier is used to energize an electromagnetic relay.

Abstract: A fail-safe acknowledging circuit having a plurality of relay switching contacts having a predetermined order of more restrictive significance. A differentiating circuit selectively interconnected by certain ones of the plurality of relay switching contacts for establishing a selected one of a plurality of charging potential levels from a d.c. voltage source. A latching circuit is conditioned by a holding voltage and is set by momentarily closure of an acknowledging switch to produce a.c. signals which are fed to one input of a two-input AND gate. A checking circuit monitors the voltage level of the d.c. voltage source and verifies the integrity of the differentiating circuit to produce a d.c. potential which is conveyed to the other input of the two-input AND gate.

Abstract: A fail-safe solid-state acknowledging circuit for a cab signaling system requiring an acknowledgment after the reception of a more restrictive speed command signal employing a plurality of transistor latching circuits having a predetermined order of more restrictive significance. Each of the transistor latching circuits is coupled to one input of a separate two input OR gate while a separate a.c. transistor amplifier is coupled to the other input of each of the two input OR gates. The outputs of the OR gates along with an acknowledging switch controlled voltage are coupled to the inputs of a multiple input AND gate for normally holding the AND gate in a signal passing condition and for causing the AND gate to assume a signal blocking condition when a more restrictive speed command signal is received onboard a vehicle.

Abstract: This disclosure relates to a fail-safe timing circuit having a regulator which produces a regulated d.c. voltage when a switch is closed. A signal generator powered by the regulated d.c. voltage for producing square-wave signals. A two-stage amplifier for amplifying the square-wave signals which are fed to a dual rectifier network which produces a positive d.c. voltage and a regulated negative fail-safe d.c. voltage. A pulse generator powered by the positive d.c. voltage for producing signal pulses having an unequal duty cycle. A charging circuit connected to the regulated negative d.c. voltage, and a trigger circuit for periodically sampling the potential charge on the charging circuit. An amplifier for amplifying periodic pulses which are produced during the sampling of the potential charge. A level detector for producing a.c. oscillations when the level of the periodic pulses exceeds a predetermined value, an amplifier for amplifying the a.c. oscillations, and a rectifier for rectifying the amplified a.c.

Abstract: A fail-safe "OR" logic gate circuit which includes at least a first and a second level detector each of which has a voltage breakdown device and an oscillating circuit, a resonant tank circuit connected in common with each of the oscillating circuits, an amplifying circuit coupled to each oscillating circuit, and a regulating-rectifying circuit coupled to the amplifying circuit and producing a d.c. output signal when a d.c. input signal causes either or both of the voltage breakdown devices to breakdown and to exhibit a low impedance for causing the oscillating circuits to oscillate and supply a.c. signals to the amplifying circuit for rectification by the regulating-rectifying circuit.

Abstract: A fail-safe symmetrical solid-state polarized relay circuit having a positive and a negative level detector coupled to a source of periodic input signals. A pair of amplifiers for amplifying the a.c. oscillations produced by the level detectors. A plurality of rectifiers for rectifying the a.c. oscillations and for alternately producing a d.c. output voltage on a pair of output terminals in accordance with the positive and negative excursions of the periodic input signals.

Abstract: This disclosure relates to a fail-safe time delay circuit for providing a definite time interval. The time delay circuit includes a resistance-capacitance charging network which is connected to a source of a d.c. supply source by a switching device. The potential charge developed on the capacitor powers an inverter to produce a.c. signals having a given frequency. The a.c. signal is fed to a multi-stage tuned amplifier having a resonant circuit tuned to the given frequency. The amplified a.c. signals are applied to a voltage doubling network which normally energizes a load and which maintains the load energized for no longer than the definite time interval after the opening of the switching device.

Abstract: This invention relates to a highly reliable and relatively noise immune electronic pulse generating circuit employing a low gain transistorized trigger circuit having its input coupled to a source of A.C. input signals and having its output coupled to a differentiating circuit for producing a single sharp narrow pulse during each cycle of the A.C. input signals.

Abstract: This disclosure relates to a fail-safe constant amplitude signal generator including a shunt regulator for supplying d.c. operating potential to a free-running transistor oscillator as well as for controlling the quality factor of a resonant tuned circuit and, in turn, the oscillator so that an a.c. output signal is capable of being produced with a known amplitude which cannot be changed by any critical circuit or component failure.

Abstract: This disclosure relates to an improved fail-safe electronic filter circuit including a common-emitter transistor amplifier having a feedback path. The feedback path includes an R-C twin-T network which is imperfectly nulled to only provide regeneration at a preselected frequency. An emitter-follower circuit operates to isolate the series resistance branch of the R-C twin-T network from the collector of the transistor amplifier so that an output signal is only available during the presence of a signal having the preselected frequency and in the absence of a critical component or circuit failure.