Abstract: A hierarchical compression tester and associated method employs a grid-based storage capacity wherein a storage unit is defined by a grouping of data blocks. Each data block is stored in one of a plurality of storage devices. Each stored data block has a data portion and a data integrity field (DIF) including a data reliability qualifier (DRQ) indicating whether the respective data portion is valid. The tester also has a logical device allocation map that includes a storage unit descriptor array that identifies one or more storage units corresponding to a selected logical address. The logical device allocation map has a DIF array that identifies whether any of the data blocks in the one or more storage units corresponding to the selected logical address includes invalid data.

Abstract: A hierarchical compression tester and associated method stored in a computer readable medium employs a grid-based storage capacity wherein a storage unit is defined by a grouping of data blocks. Each data block is stored in one of a plurality of storage devices. Each stored data block has a data portion and a data integrity field (DIF) including a data reliability qualifier (DRQ) indicating whether the respective data portion is valid. The tester also has a logical device allocation map that includes a storage unit descriptor array that identifies one or more storage units corresponding to a selected logical address. The logical device allocation map has a DIF array that identifies whether any of the data blocks in the one or more storage units corresponding to the selected logical address includes invalid data.

Abstract: Method and apparatus for providing a visual indication of operational activity of a device, such as a selected data transfer state. A pattern generator provides one or more bitmasks, each comprising a selected multi-bit sequence of logical values. A switching circuit selectively activates a visual indicator, such as a light emitting diode (LED), to provide a different visual indication in relation to each bitmask. Preferably, a time-varying rate at which the visual indicator is activated in response to each bitmask is selected to be different from a rate, as perceived by a human observer, of activation of the indicator. The pattern generator is preferably implemented as a programming module in a memory space and executed by a processor. Alternatively, the pattern generator is implemented in hardware preferably through the use of an index table and shift register circuitry.