Abstract: The present invention is a spark gap protection capable of integrating into multiple layer semiconductor substrate packaging. The initial gap in the spark gap is solid and it can be converted into air, meaning gaseous, and the air gap is achieved by having the gap initially be filled with a solid and then running a voltage through the spark gap so that the gap explodes and the solid is replaced by an air cavity.

Abstract: A hybrid magnetic material comprising at least one magnetic material having at least one internal porous insulative layer; and wherein, at least one of the magnetic materials fills the voids of the internal porous insulative layer. The hybrid material blends core metals and insulation layers in a manner so that the resulting material operates as a single layer material with its own unique conductivity; skin effect; B-H curve; BSAT parameters; and a unique and strong directional impedance. By using a porous insulation layer, metal layers may be bonded together through insulation layers, and this allows rapid low cost formation of the hybrid material. The hybrid material may be used to form small low-cost cores capable of handling high frequency applications.

Abstract: In an exemplary embodiment of the present invention: A series of U-shaped nickel-iron components are plated onto a rough or roughened semiconductor package or printed circuit board material. The horizontal base of the U-shaped component has a surface roughness of the semiconductor package material. The vertical surfaces of the U-shape have a surface roughness derived from the dry film. The large smooth vertical surface allows the U-shaped nickel-iron components to have a low average roughness. The lowered average roughness reduces the path length the U-shaped nickel-iron components provide for magnetic flux while the roughness of the horizontal portion of the U-shape allows for increased mechanical bonding to occur.

Abstract: A hybrid conductive material comprising at least one conductive material having at least one internal porous insulative layer; and wherein, at least one of the conductive materials fills the voids of the internal porous insulative layer. The hybrid material blends conductive metals and porous insulation layers in a manner so that the resulting material operates as a single layer material with its own unique conductivity and skin depth; and a unique and strong directional impedance. By using a porous insulation layer, metal layers may be bonded together through insulation layers, and this allows rapid low-cost formation of the hybrid material. The hybrid material may be used to form thin wires or traces capable of handling high frequency applications.

Abstract: The present invention is a spark gap protection capable of integrating into multiple layer semiconductor substrate packaging. The initial gap in the spark gap is solid and it can be converted into air, meaning gaseous, and the air gap is achieved by having the gap initially be filled with a solid and then running a voltage through the spark gap so that the gap explodes and the solid is replaced by an air cavity.

Abstract: The present invention comprises a specially designed means of air gap optimization for magnetically permeable material used in electrical components, for example, inductors and transformers. First, an ideal inductance over current curve is selected, and a core start point, endpoint, start angle, and end angle are selected within the core or along the core edges. Given the ideal curve and the starting conditions, an air gap is designed which meets or comes as close as possible to the ideal curve selected. Multiple air gaps can be designed in a single core. The inclusion of novel partial air gaps enables curves to be reached that optimize the core for high and low currents.

Abstract: A new method and apparatus for wafer-level electroplating that allows for the plating of pillars, inductors, windings, and other components not easily plated in plating wafer level chip scale packaging with ball connectors. By plating pillars directly onto a silicon wafer, covering both pillar and wafer with dielectric film, and grinding to expose the copper pillar, integrated circuits which incorporate passive components can be directly created on the wafer before any singulation.

Abstract: A method of producing layered cores for magnetic circuit components such as inductors and transformers suitable for use in the microelectronics industry. A series of pillars are created on a carrier Layers of the magnetic core are plated onto the exposed surface of the pillars. After the desired number of core layers are plated, the plated layers are ground down to expose the pillars, leaving a series of magnetic cores between the pillars. The pillars can then be removed, leaving a series of magnetic cores. The pillars are created by either building up pillars, such as copper pillars, or by slitting plastic mediums, such as dry film or epoxy plastic, the roughness of the magnetic cores produced depends on the method of forming the pillars.

Abstract: An apparatus and method for plating magnetic cores by periodically transferring a plate directly back and forth between a metal plating environment and an insulation deposit environment. This direct metal to insulation to metal plating is enabled by a nano-scale insulation layer that provides an imperfect coverage of the metal layer while still keeping sufficient insulation to prevent eddy current formation—even during high-frequency current applications. Therefore, this invention enables the practical creation of magnetic cores having layers with widths even under one nanometer and can generate cores having a layer scale that can be varied to suit a variety of uses in the microelectronic industry.

Abstract: A complex-shaped air gap for electrical components utilizing magnetically permeable material. The air is enabled to thermally distribute heat through a magnetic core and thus reduce issues relating to heat localization. The air gap shape is maximized for length, and in the preferred embodiment is a spiral shape. The preferred embodiment is built by a lithography process, without cutting, to enable the thin spiraling shape.

Abstract: A security integrated circuit is disclosed. In some embodiments, the security integrated circuit comprises metal configured memory that stores a first portion of each of a plurality of keys, programmable memory that stores a second portion of each of the plurality of keys, and an interface for connecting to an external authentication system. The metal configured memory and programmable memory store a prescribed finite number of host keys and matching device keys. In response to a received host key from the external authentication system, a matching device key is provided by the security integrated circuit.

Abstract: A low cost, high efficiency light-emitting diode design is disclosed. In some embodiments, a p-n junction of a light-emitting diode is formed in an epitaxial layer grown on a substrate. Grinding the backside of an associated wafer after encapsulation not only opens a light path for the light emitting diode but removes most residual defects.

Abstract: A single integrated circuit that supports both power switching and data switching is disclosed. In some embodiments, the integrated circuit comprises a driver circuit configured to drive a switch of an associated line in a power mode or in a data mode and one or more decoupling capacitor ground switches, wherein each decoupling capacitor ground switch connects an associated decoupling capacitor to ground in the power mode and wherein each decoupling capacitor ground switch leaves an associated decoupling capacitor floating in the data mode.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: Various techniques for dynamic power FET switching are disclosed. In some embodiments, a device comprises an array of two or more independently switchable power MOSFETs that are configured to sense current in a high current mode and a low current mode as well as circuitry for automatically switching from the low current mode to the high current mode when sensed current is above a threshold to switch to the high current mode.

Abstract: A four pin integrated circuit MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) load switch is disclosed that provides full features including adjustable ramp time/rate, adjustable discharge time/rate, temperature control, over-current control, and short circuit protection. In some embodiments, the adjustable ramp is based on the voltage or current input into the integrated circuit.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.