Abstract: Passivation coatings and gettering agents may be used in an Extreme Ultraviolet (EUV) source which uses tin (Sn) vapor as a plasma “fuel” to prevent contamination and corresponding loss of reflectivity due to tin contamination. The passivation coating may be a material to which tin does not adhere, and may be placed on reflective surfaces in the source chamber. The gettering agent may be a material that reacts strongly with tin, and may be placed outside of the collector mirrors and/or on non-reflective surfaces. A passivation coating may also be provided on the insulator between the anode and cathode of the source electrodes to prevent shorting due to tin coating the insulator surface.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: Methods of forming a microelectronic structure are described. Those methods include forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer includes a coefficient of thermal expansion that is approximately between the coefficient of thermal expansion of the first adhesion layer and the coefficient of thermal expansion of the barrier layer.

Abstract: Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.

Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a high-k gate dielectric layer that includes impurities, then forming a silicon containing sacrificial layer on the high-k gate dielectric layer. After the silicon containing sacrificial layer has gettered the impurities from the high-k gate dielectric layer, the silicon containing sacrificial layer is removed, and a gate electrode is formed on the high-k gate dielectric layer. The method optionally includes exposing the high-k gate dielectric layer to a silicic acid containing solution until a silicon dioxide capping layer forms on the high-k gate dielectric layer, prior to forming a gate electrode on the capping layer.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a high-k gate dielectric layer that includes impurities, then forming a silicon containing sacrificial layer on the high-k gate dielectric layer. After the silicon containing sacrificial layer has gettered the impurities from the high-k gate dielectric layer, the silicon containing sacrificial layer is removed, and a gate electrode is formed on the high-k gate dielectric layer. The method optionally includes exposing the high-k gate dielectric layer to a silicic acid containing solution until a silicon dioxide capping layer forms on the high-k gate dielectric layer, prior to forming a gate electrode on the capping layer.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a high-k gate dielectric layer that includes impurities, then forming a silicon containing sacrificial layer on the high-k gate dielectric layer. After the silicon containing sacrificial layer has gettered the impurities from the high-k gate dielectric layer, the silicon containing sacrificial layer is removed, and a gate electrode is formed on the high-k gate dielectric layer. The method optionally includes exposing the high-k gate dielectric layer to a silicic acid containing solution until a silicon dioxide capping layer forms on the high-k gate dielectric layer, prior to forming a gate electrode on the capping layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: A method for making a semiconductor device is described. That method comprises forming a nitride based sacrificial layer on a high-k gate dielectric layer to transfer nitrogen from the nitride based sacrificial layer to the high-k gate dielectric layer to form a nitridized high-k gate dielectric layer. The remaining sacrificial layer is then removed from the nitridized high-k gate dielectric layer using a wet etch process that comprises exposing the remaining sacrificial layer to a solution that contains a non-metallic hydroxide. A gate electrode is then formed on the nitridized high-k gate dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type.

Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type.