Patents by Inventor John P. Bates
John P. Bates has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870252Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.Type: GrantFiled: November 13, 2013Date of Patent: January 16, 2018Assignee: Sony Interactive Entertainment Inc.Inventor: John P. Bates
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Publication number: 20140075450Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.Type: ApplicationFiled: November 13, 2013Publication date: March 13, 2014Applicant: Sony Computer Entertainment Inc.Inventor: John P. Bates
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Patent number: 8589943Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.Type: GrantFiled: August 15, 2007Date of Patent: November 19, 2013Assignee: Sony Computer Entertainment Inc.Inventor: John P. Bates
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Patent number: 8171235Abstract: An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on an address in main memory. The address has a size less than or equal to a maximum memory transfer size for the second processor and greater than a maximum memory transfer size for the first processor. The second processor atomically performs the compare and swap operation and notifies the first processor of the success or failure of the compare and swap operation.Type: GrantFiled: January 28, 2009Date of Patent: May 1, 2012Assignee: Sony Computer Entertainment Inc.Inventors: James E. Marr, John P. Bates
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Patent number: 8161094Abstract: Methods are provided for event notification in a decentralized peer-to-peer (P2P) network. Each node within the P2P network can publish a subscription object for a published resource. Through the use of common identifiers, each subscription object is co-located with a corresponding publish object for the resource. Upon receiving notification of an event associated with the resource, the node responsible for the publish object for the resource distributes the event notification to each node present on the corresponding subscription registry. Therefore, nodes within the P2P network that are interested in a resource are capable of establishing a persistent query for the resource by publishing a subscription object for the resource on the responsible node.Type: GrantFiled: May 27, 2004Date of Patent: April 17, 2012Assignee: Sony Computer Entertainment Inc.Inventors: Payton R. White, John P. Bates, Howard Berkey
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Patent number: 8141076Abstract: Methods and apparatus for cell processors are disclosed. A policy module is loaded from a main memory of a cell processor into the local memory of a selected synergistic processing unit (SPU) under control of an SPU policy module manager (SPMM) running on the SPU. The policy module loads a work queue from the main memory into the local memory of the SPU. The policy module interprets and process one or more tasks from the work queue on the SPU. The selected SPU performs the task(s) and after completion or upon a pre-emption, returns control of the SPU to the SPMM.Type: GrantFiled: September 27, 2005Date of Patent: March 20, 2012Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Payton R. White, Attila Vass
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Patent number: 8068109Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs. The two or more outputs are associated into one or more groups. Each group is less than or equal to a target data size associated with a subsequent process.Type: GrantFiled: June 8, 2010Date of Patent: November 29, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Richard B. Stenson, John P. Bates
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Patent number: 8037271Abstract: Methods copying data from one location to another in a main memory of a cell processor are disclosed. A portion of the data is transferred a first main memory location to the local store of one or more SPU and then transferred from the local store to a second main memory location.Type: GrantFiled: February 17, 2009Date of Patent: October 11, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Antoine Labour, Richard B. Stenson, John P. Bates
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Patent number: 8037474Abstract: Cell processor task management in a cell processor having a main memory, one or more power processor units (PPU) and one or more synergistic processing units (SPU), each SPU having a processor and a local memory is described. An SPU task manager (STM) running on one or more of the SPUs reads one or more task definitions stored in the main memory into the local memory of a selected SPU. Based on information contained in the task definitions the SPU loads code and/or data related to the task definitions from the main memory into the local memory associated with the selected SPU. The selected SPU then performs one or more tasks using the code and/or data.Type: GrantFiled: September 27, 2005Date of Patent: October 11, 2011Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Payton R. White, Richard B. Stenson, Howard Berkey, Atilla Vass, Mark Cerny, John Morgan
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Patent number: 8024521Abstract: Atomic operation may be implemented in a processor system comprising a main memory and a power processor element (PPE) including a power processor unit (PPU) coupled to an external cache. The PPE may atomically load data from a lock-line in the main memory into a first location X in the external cache. A size of the data and the lock line may be larger than a data size for the standard atomic operations that may be performed with the PPE. The data may be reserved in a second location Y in the external cache.Type: GrantFiled: March 13, 2007Date of Patent: September 20, 2011Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, James E. Marr, Attila Vass
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Patent number: 7979680Abstract: A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/or data for a second context in a second region of the local memory, the secondary processor may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the processor may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another processor's local memory.Type: GrantFiled: December 3, 2009Date of Patent: July 12, 2011Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Attila Vass
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Patent number: 7975269Abstract: Methods and apparatus for parallel processors are disclosed. A policy module is loaded from a main memory of a processor into the local memory of a selected secondary processing element under control of a policy module manager running on the secondary processing element. A selected one or more work queues are assigned from a main memory to a selected one or more of the secondary processing elements according to a hierarchy of precedence. A policy module for the selected one or more work queues is loaded to the selected one or more secondary processing elements. The policy module interprets the selected one or more of the selected one or more work queues. Under control of the policy module, work from one or more of the selected one or more work queues is loaded into the local memory of the selected secondary processing element. The work is performed with the selected secondary processing element.Type: GrantFiled: July 31, 2006Date of Patent: July 5, 2011Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Keisuke Inoue, Mark E. Cerny
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Patent number: 7941482Abstract: A method of dynamically balancing a load on a fully connected grid (FCG) in a peer-to-peer environment includes determining if a first number of peers connected in a first FCG is greater than a preselected limit. If the first number of peers connected to the first FCG is greater than the preselected limit, then partitioning the first FCG into two or more subdivided FCGs, wherein each of the subdivided FCGs includes at least one peer connection that was previously connected in the first FCG. A subdivided location identifier can also be published for each respective resource included in each peer connection. A system for dynamically balancing a load on a fully connected grid (FCG) in a peer-to-peer environment is also described.Type: GrantFiled: April 26, 2004Date of Patent: May 10, 2011Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Howard Berkey
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Publication number: 20100251245Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs. The two or more outputs are associated into one or more groups. Each group is less than or equal to a target data size associated with a subsequent process.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Applicant: Sony Computer Entertainment Inc.Inventors: Richard B. Stenson, John P. Bates
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Publication number: 20100235845Abstract: A method for processing of processor executable tasks and a processor readable medium having embodied therein processor executable instructions for implementing the method are disclosed. A system for distributing processing work amongst a plurality of distributed processors is also disclosed. A task generated with a local node is divided into one or more sub-tasks. An optimum number of nodes x on which to process the sub-tasks is determined If x is greater than one a determination is made to either (1) execute the task at the local node with the processor unit, (2), distribute the task among two or more local node processors, (3) distribute the task to one or more of the distributed nodes accessible to the local node over a LAN, or (4) distribute the task to one or more of the distributed nodes that are accessible to the local node over a WAN.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventors: John P. Bates, Payton R. White
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Patent number: 7760206Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs.Type: GrantFiled: February 13, 2009Date of Patent: July 20, 2010Assignee: Sony Computer Entertainment Inc.Inventors: Richard B. Stenson, John P. Bates
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Patent number: 7730119Abstract: A method for processing of processor executable tasks and a processor readable medium having embodied therein processor executable instructions for implementing the method are disclosed. A system for distributing processing work amongst a plurality of distributed processors is also disclosed.Type: GrantFiled: July 21, 2006Date of Patent: June 1, 2010Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Payton R. White
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Publication number: 20100082951Abstract: A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/or data for a second context in a second region of the local memory, the secondary processor may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the processor may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another processor's local memory.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: Sony Computer Entertainment Inc.Inventors: John P. Bates, Attila Vass
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Patent number: 7647483Abstract: A processor system and a processor readable medium, which implement a method for implementing multiple contexts on one or more SPE are disclosed. Code and/or data for a first and second contexts may be respectively stored simultaneously in first and second regions of an SPE's local memory, storing code and/or data for a second context in a second region of the local memory, the SPE may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the SPE may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another SPE's local memory.Type: GrantFiled: February 20, 2007Date of Patent: January 12, 2010Assignee: Sony Computer Entertainment Inc.Inventors: John P. Bates, Attila Vass
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Publication number: 20090147013Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs.Type: ApplicationFiled: February 13, 2009Publication date: June 11, 2009Applicant: Sony Computer Entertainment Inc.Inventors: Richard B. Stenson, John P. Bates