Abstract: A cryptographic apparatus for encrypting and decrypting digital words includes a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus. The storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm. A mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.

Abstract: An improved semaphore is described that arbitrates the access of a memory shared by first and second microcomputers operating asynchronously at the same speed or at different speeds. The semaphore includes a semaphore flip-flop producing a binary semaphore signal indicating whether or not the semaphore is owned, and an ownership flip-flop producing a binary ownership signal indicating which of the first or second microcomputers previously owned the semaphore. First gating circuitry decodes control signals from the first microcomputer and generates a read or write pulse signal. The read pulse signal from the first gating circuitry loads the semaphore signal and ownership signal into first and second flip-flops, respectively, whose outputs are applied to the data bus of the first microcomputer. Second gating circuitry decodes control signals from the second microcomputer and generates a read or write pulse signal.

Abstract: A method for synchronizing the scrambling sequences of communicating scrambler units of a privacy communications system in a reliable and secure manner. The method is particularly adapted for use in noisy or fade prone transmission environments, and permits late entry of authorized third parties to the system. The method utilizes digital sequences interleaved periodically with scrambled analog information to provide reliable synchronization.

Abstract: A data transmission system is described where data signals are bidirectionally transmitted between a data transmitter and a plurality of data receivers in a self-clocking bit streams carried on true data and complement data signal lines and a non-return-to-zero (NRZ) bit streams on a return data signal line. According to an inventive data transmission scheme, data signals are transmitted by the data transmitter by utilizing the four possible two-bit binary states of the true data and complement data signal lines. Of the four two-bit binary states, a word state is provided before and after the data signal and a one state or zero state followed by a bit state is provided for each bit of the data signal. The data receivers detect the bit state to recover a bit clock signal and detect the one state and zero state to recover an NRZ data signal.

Abstract: A demodulator is described for demodulating phase-encoded data signals transmitted on a noisy communication channel, such as, for example, radio communication channels of a radio communication system. The demodulator includes a digital phase-locked loop for phase-locking to the mid-bit transitions of the phase-encoded data signal, which, in the preferred embodiment is encoded according to the well known Manchester coding format, and further includes demodulating circuitry for sampling the phase-encoded data signal a predetermind number of times, weighting the samples according to predetermined weighting factors, totalizing the weighted samples for each bit interval and comparing the totalized samples to a predetermined threshold value for ascertaining the logical state of each bit of the phase-encoded data signal.