Abstract: An apparatus includes a shaft, an expandable dilator, and at least one ventilation pathway. The shaft defines a longitudinal axis and includes a distal and proximal ends with at least one shaft lumen. The expandable dilator includes body with its own proximal and distal ends. The body is configured to transition between a contracted state and an expanded state. The body is configured to dilate a Eustachian tube of a patient in the expanded state. The at least one ventilation pathway is configured to provide ventilation from the distal end of the body to the proximal end of the body when the body is in the expanded state. In some examples, the ventilation pathway includes a set of transversely oriented vent openings formed through the shaft. In some other examples, the ventilation pathway includes a space defined between one or more radially outwardly protruding features of the expandable dilator.

Abstract: An injector is disclosed for injecting an injectable substance into at least one of the epidermal tissue and the dermal tissue of a subject. The injector includes an outer housing and a control member disposed within the outer housing. A needle head, which is configured to support a plurality of needles, is operatively coupled to the control member. First means are provided in communication with the control member and are configured to be driven by the control member for converting a movement of the control member into a movement of the needle head along an injection direction and toward an injecting position of the needle head. Second means are configured to move the needle head in a direction having a component that is normal to the injection direction and absent movement of the outer housing relative to the skin of the subject.

Abstract: An integrated circuit with copper damascene interconnects includes a thin film resistor. Copper damascene metal lines are formed in a first ILD layer. A dielectric layer including an etch stop layer is formed on the first ILD layer and metal lines. Resistor heads of refractory metal are formed in the dielectric layer so that edges of the resistor heads are substantially coplanar with the adjacent dielectric layer. A thin film resistor layer is formed on the dielectric layer, extending onto the resistor heads. A second ILD layer is formed over the dielectric layer and the thin film resistor layer. Copper damascene vias are formed in the second ILD layer, making contact to the metal lines in the first ILD layer. Connections to the resistor heads are provided by the metal lines and/or the vias.

Abstract: Systems and methods that extend the use of data mining to identify students academically at risk of performing poorly or withdrawing from school altogether. In doing so, academically at-risk students are identified early and guided to resources to improve their academic performance.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: The present disclosure is directed to a process for plasma treating a film comprising titanium, nitrogen and impurities on a substrate. The process comprises forming a plasma of nitrogen gas and hydrogen gas, the flow ratio of hydrogen gas to nitrogen gas ranging from about 0.01 to about 0.7. The film is contacted with the plasma for a time sufficient to reduce the concentration of impurities in the film.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug.

Abstract: A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.

Abstract: A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.