Patents by Inventor John P. Devale

John P. Devale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory array on more than one die
    Patent number: 8059441
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: November 15, 2011
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Prefetching from dynamic random access memory to a static random access memory
    Patent number: 8032711
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Bryan Black, Murali M. Annavaram, Donald W. McCauley, John P. Devale
  • MEMORY ARRAY ON MORE THAN ONE DIE
    Publication number: 20100149849
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Inventors: Mohammed Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Memory array on more than one die
    Patent number: 7692946
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • MEMORY ARRAY ON MORE THAN ONE DIE
    Publication number: 20090001601
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Jeffrey P. Rupley, II, Edward A. Brekelbaum, Gabriel H. Loh, Bryan Black
  • Multi-purpose register cache
    Patent number: 7418551
    Abstract: A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: John P. DeVale, Bryan P. Black, Edward A. Brekelbaum, Jeffrey P. Rupley, II
  • Prefetching from dynamic random access memory to a static random access memory
    Publication number: 20080155196
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Bryan Black, Murali M. Annavaram, Donald W. McCauley, John P. Devale
  • Predictive filtering of register cache entry
    Patent number: 7171545
    Abstract: A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: John P. Devale, Bryan P. Black, Edward A. Brekelbaum, Jeffrey P. Rupley, II