Patents by Inventor John P. Didier

John P. Didier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10921987
    Abstract: A method of performing deduplication includes (1) receiving a write command that specifies a set of data, the set of data including multiple blocks of data, (2) hashing a subset of the set of data, yielding a representative digest of the set of data, and (3) performing deduplication on the set of data based at least in part on matching the representative digest to a digest already stored in a database which relates digests to locations of data from which the digests were produced. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, John P. Didier, Sorin Faibish
  • Publication number: 20210034249
    Abstract: A method of performing deduplication includes (1) receiving a write command that specifies a set of data, the set of data including multiple blocks of data, (2) hashing a subset of the set of data, yielding a representative digest of the set of data, and (3) performing deduplication on the set of data based at least in part on matching the representative digest to a digest already stored in a database which relates digests to locations of data from which the digests were produced. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Philippe Armangau, John P. Didier, Sorin Faibish
  • Patent number: 10678480
    Abstract: Technology for dynamically adjusting a process scheduler in a storage processor of a data storage system. An average amount of host data contained in sets of host data processed by host I/O request processing threads is calculated. An average amount of time required for each host I/O request processing thread to execute to completely process the average amount of host data contained in a set of host data is also calculated. Operation of the process scheduler in the storage processor is then adjusted to cause the process scheduler to subsequently allocate the processor in the storage processor to host I/O request processing threads in timeslices having a duration that is at least as large as the average amount of time required for each host I/O request processing thread to execute to completely process the average amount of host data contained in a set of host data.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Bruce A. Zimmerman, John P. Didier, Rustem Rafikov
  • Patent number: 7624206
    Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 24, 2009
    Assignee: EMC Corporation
    Inventors: Adrianna D. Bailey, John V. Burroughs, John P. Didier, Morrie Gasser, Douglas E. Peeke, Matthew Long
  • Publication number: 20080126631
    Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.
    Type: Application
    Filed: September 29, 2005
    Publication date: May 29, 2008
    Inventors: Adrianna D. Bailey, John V. Burroughs, John P. Didier, Morrie Gasser, Douglas E. Peeke, Matthew Long