Patents by Inventor John P. Erdeljac
John P. Erdeljac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9431286Abstract: A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.Type: GrantFiled: November 26, 2014Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P Pendharkar, Binghua Hu, Abbas Ali, Henry Litzmann Edwards, John P. Erdeljac, Britton Robbins, Jarvis Benjamin Jacobs
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Patent number: 6683380Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.Type: GrantFiled: July 10, 2002Date of Patent: January 27, 2004Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Donald C. Abbott, Walter Bucksch, Marco Corsi, Chi-Cheong Shen, John P. Erdeljac, Louis N. Hutter, Quang X. Mai, Konrad Wagensohner, Charles E. Williams, Milton L. Buschbom
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Patent number: 6534364Abstract: A tunnel diode construction 12 for an EEPROM device 10, and method for making it are shown. A tank 13 is provided at a surface of a semiconductor substrate 5 containing a doped diffused tunnel region 46. A layer of insulation 38 is provided over the surface of the substrate with a first thickness 48 to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness 39 elsewhere. A conducting floating gate 19 is provided above the doped diffused tunnel region 46 and at least part of the tank 13, on the layer of insulation 38. The floating gate 19 extends over the oxide 38 beyond the lateral boundaries of the doped diffused tunnel region 46 in every direction to terminate over the second thickness of oxide 39 over the tank 13.Type: GrantFiled: October 14, 1997Date of Patent: March 18, 2003Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter
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Publication number: 20030036256Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.Type: ApplicationFiled: July 10, 2002Publication date: February 20, 2003Inventors: Taylor R. Efland, Donald C. Abbott, Walter Bucksch, Marco Corsi, Chi-Cheong Shen, John P. Erdeljac, Louis N. Hutter, Quang X. Mai, Konrad Wagensohner, Charles E. Williams, Milton L. Buschbom
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Patent number: 6424005Abstract: An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.Type: GrantFiled: December 3, 1998Date of Patent: July 23, 2002Assignee: Texas Instruments IncorporatedInventors: Chin-Yu Tsai, Taylor R. Efland, Sameer Pendharkar, John P. Erdeljac, Jozef Mitros, Jeffrey P. Smith, Louis N. Hutter
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Publication number: 20010019865Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.Type: ApplicationFiled: February 2, 2001Publication date: September 6, 2001Inventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
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Patent number: 6284617Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.Type: GrantFiled: February 2, 2001Date of Patent: September 4, 2001Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
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Patent number: 6284669Abstract: A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).Type: GrantFiled: October 7, 1998Date of Patent: September 4, 2001Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter, Jeffrey P. Smith, Han-Tzong Yuan, Jau-Yuann Yang, Taylor R. Efland, C. Matthew Thompson, John K. Arch, Mary Ann Murphy
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Patent number: 6236101Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.Type: GrantFiled: October 30, 1998Date of Patent: May 22, 2001Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
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Patent number: 6153451Abstract: A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.Type: GrantFiled: January 5, 1998Date of Patent: November 28, 2000Assignee: Texas Instruments IncorporatedInventors: Louis N. Hutter, John P. Erdeljac, Jeffrey P. Smith
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Patent number: 6144100Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.Type: GrantFiled: October 28, 1997Date of Patent: November 7, 2000Assignee: Texas Instruments IncorporatedInventors: Chi-Cheong Shen, Donald C. Abbott, Walter Bucksch, Marco Corsi, Taylor Rice Efland, John P. Erdeljac, Louis Nicholas Hutter, Quang Mai, Konrad Wagensohner, Charles Edward Williams
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Patent number: 6025231Abstract: A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).Type: GrantFiled: February 18, 1998Date of Patent: February 15, 2000Assignee: Texas Instruments IncorporatedInventors: Louis N. Hutter, John P. Erdeljac, James R. Todd
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Patent number: 5825065Abstract: A method of fabricating a semiconductor device containing a HVDMOS transistor and a LVDMOS transistor and the device which includes providing a region of semiconductor material of a first conductivity type and forming a high voltage DMOS transistor disposed in the region. A relatively low voltage DMOS transistor is also disposed in that region and electrically isolated from the high voltage DMOS transistor. The low voltage DMOS transistor has spaced apart source and drain regions disposed in the region of semiconductor material and a back gate region of the first conductivity type disposed in the region of semiconductor material between the source and drain regions. The back gate region is electrically coupled to the region of semiconductor material. The region of semiconductor material includes a surface, the source, drain and back gate regions extending to that surface.Type: GrantFiled: January 14, 1997Date of Patent: October 20, 1998Assignee: Texas Instruments IncorporatedInventors: Marco Corsi, Louis N. Hutter, John P. Erdeljac
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Patent number: 5719421Abstract: A DMOS transistor (50) includes an Nwell (70); a Dwell (76) formed in the Nwell (70); a source region (78) formed in the Dwell (78), a channel region (80) defined between an edge of the source region (78) and an edge of the Nwell (70); a gate (86) extending over the channel region (80); and a p+ backgate contact region (90) formed in the source region (78) so as to counterdope and extend through a first portion of the source region (78) to contact the Dwell (76). The formation of the p+ backgate contact region through the source region (78) eliminates the need for a large annular shaped source region resulting in a considerable reduction in both device area and on-resistance.Type: GrantFiled: December 31, 1996Date of Patent: February 17, 1998Assignee: Texas Instruments IncorporatedInventors: Louis N. Hutter, John P. Erdeljac
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Patent number: 5576233Abstract: A method for making an EEPROM (10) in a semiconductor substrate (40) and EEPROM made according to the method includes forming a gate dielectric (38), such as oxide, nitride, multilayer dielectric, or the like, on a surface of the substrate (40) and forming a polysilicon floating gate (19) on the gate dielectric (38). A control gate (25) is formed at least partially overlying the floating gate (19), and a thermal oxide layer (56) is formed on the floating gate (19) in regions that are not covered by the control gate. Thus, the thermal oxide layer (56) encases any regions of the floating gate (19) uncovered by the control gate (25) and serves as a high quality dielectric to isolate the floating gate (19) from charge loss and other deleterious effects. Then, source and drain regions (21,27) are formed in the substrate (40).Type: GrantFiled: June 21, 1995Date of Patent: November 19, 1996Assignee: Texas Instruments IncorporatedInventors: Louis N. Hutter, John P. Erdeljac
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Patent number: 5554873Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).Type: GrantFiled: June 7, 1995Date of Patent: September 10, 1996Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter
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Patent number: 5489547Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).Type: GrantFiled: May 23, 1994Date of Patent: February 6, 1996Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter
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Patent number: 5436179Abstract: A bipolar transistor is formed on a substrate of a first (P) conductivity type by: forming a collector region (20) of the second conductivity type (N) in the substrate; forming an adjust region (27) of the first (P) conductivity type in the collector region (20); forming a base region (36) of the first (P) conductivity type in the collector region (20), the base region (36) containing the adjust region (27); and forming an emitter region (11) of the second (N) conductivity type in the adjust region (27). The base region (36) is deeper than and more heavily doped than the adjust region (27). The adjust region (27) alters the doping profile of the base-collector junction on the collector (20) side of the junction to increase the breakdown voltage of the transistor.Type: GrantFiled: January 5, 1994Date of Patent: July 25, 1995Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter
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Patent number: 5408125Abstract: A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substantially smaller dosage of a faster-diffusing dopant of the second conductivity type is then implanted into the buried layer region. The second epitaxial layer of the first conductivity type is formed over the first epitaxial layer. A region of the second epitaxial layer overlying the doped region of the first epitaxial layer is implanted with a dopant of the second conductivity type and diffused to form a doped well. The faster-diffusing dopant diffuses upward to make good electrical contact with the doped well diffusing downward from the surface. The lateral diffusion of the faster-diffusing dopant can be contained, so that lateral spacing design rules do not have to be increased.Type: GrantFiled: January 4, 1994Date of Patent: April 18, 1995Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter
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Patent number: 5330922Abstract: A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substantially smaller dosage of a faster-diffusing dopant of the second conductivity type is then implanted into the buried layer region. The second epitaxial layer of the first conductivity type is formed over the first epitaxial layer. A region of the second epitaxial layer overlying the doped region of the first epitaxial layer is implanted with a dopant of the second conductivity type and diffused to form a doped well. The faster-diffusing dopant diffuses upward to make good electrical contact with the doped well diffusing downward from the surface. The lateral diffusion of the faster-diffusing dopant can be contained, so that lateral spacing design rules do not have to be increased.Type: GrantFiled: September 25, 1989Date of Patent: July 19, 1994Assignee: Texas Instruments IncorporatedInventors: John P. Erdeljac, Louis N. Hutter