Abstract: A programmable communications processor is coupled to execute instructions of programs designed to process the transfer of information between a plurality of communication channels and a main memory included in the system. A software implemented and controlled pause counter enables the execution of a given maximum number of instructions for servicing, for example, a communication channel following which it suspends or pauses such servicing, in order to service another higher priority request which may be pending. Processing of lower priority service requests thus cannot delay the recognition and handling of higher priority requests for more than a minimum period of time and the effective throughput rate is increased.

Abstract: A communication processor is coupled to recognize and handle on a priority basis, service interrupt requests from a plurality of communication line adapters. The processor is also adapted to perform a firmware-controlled scan of the communication line adapters, completely independently of any data transfers involving such adapters, to determine the status of the communication lines handled thereby and, on detection of a status which is changed from a previously stored status, to store the new status in the processor and take any action necessary as indicated by a command previously stored in the processor.

Abstract: Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.

Abstract: A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.

Abstract: Data is transferred between a main memory in a data processing system and communication channels under the control of communications control blocks provided in an auxiliary memory, each of which control blocks includes a starting address, range and status information so as to enable the transfer of data to data blocks included in the main memory as indicated by the starting address in the control blocks. A predetermined number of control blocks is allocated in the auxiliary memory for each communications channel and the transfer of all such data is performed utilizing as many of the predetermined number of control blocks as required for the channel until the transfer is complete as indicated by the last such control block utilized in the transfer. Control blocks are loaded in the auxiliary memory under control of the central processor of the system and are periodically accessed by the processor to determine the status of data transfer operations.