Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

Abstract: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.

Abstract: The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.

Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.

Abstract: Patterning metal stack layers of a magnetic switching device to enable a critical lithography level to be made on planar substrate without any topography and enable a second lithography step without topography from a top patterned hardmask, comprising:

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.

Abstract: A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.

Abstract: A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper.

Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.