Abstract: The present invention relates to compounds that inhibit KRas G12C. In particular, the present invention relates to compounds that irreversibly inhibit the activity of KRas G12C, pharmaceutical compositions comprising the compounds and methods of use therefor.

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

Abstract: A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Abstract: In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

Abstract: Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

Abstract: Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Abstract: Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Abstract: Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Abstract: Embodiments of the present invention provide a method and apparatus for implementing fault detection and correction in a computer network. In one embodiment, the invention may provides a multi-stage watch-dog timer to monitor device operation in a computer system. A system bus controller may receive data related to a computer system fault from the multi-stage watch-dog timer and may log the fault data in memory. The system bus controller may also forward the fault data to an external server. In an alternative embodiment, the invention provides a processor that may re-set the multi-stage watch-dog timer at pre-determined intervals during normal operation. In yet another alternative embodiment, the processor may receive an interrupt from the watch-dog timer if at least one stage of the multi-stage watch-dog timer is not re-set during the fault and the processor may further run a diagnostic test to find the fault.

Abstract: Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Abstract: Embodiments of the present invention relate to providing system management and control of chipset modules using an external micro controller. In an embodiment of the present invention, a SMB buffer read command including a buffer address may be received from an external micro-controller. Internal bus access may be requested from a bus arbiter. If bus access is granted, the SMB buffer read command may be sent to a module identified by the buffer address. The module is at least one of a plurality of modules having an associated data buffer to log data related to the operation of the module. The contents of the data buffer associated with the module may be received and forwarded to the external micro-controller.

Abstract: Embodiments of the present invention provide a method and apparatus for receiving an input command over a system management bus, and, in response, simulating an existing signal which, when present, generates an interrupt. The interrupt, when received by the processor, triggers an operating system controlled shutdown of the computer system.

Abstract: Disclosed is an adjustable length rotary drive coupling comprising a first rotary shaft provided with at least one tooth and a second rotary shaft provided with a plurality of abutment surfaces spaced apart along the length thereof associated with each the tooth. One of the rotary shafts is a drive shaft, with the other shaft being a driven shaft. Each tooth is selectively engageable with any of its associated abutment surfaces, to enable the length of the rotary drive coupling to be adjusted.

Abstract: An adjustable length rotary drive coupling comprising a first rotary shaft provided with at least one tooth and a second rotary shaft provided with a plurality of abutment surfaces spaced apart along the length thereof associated with each the tooth. One of the rotary shafts is a drive shaft, with the other shaft being a driven shaft. Each tooth is selectively engageable with any of its associated abutment surfaces, to enable the length of the rotary drive coupling to be adjusted.

Abstract: A gas-powered paint ball gun in which a magazine is attached tangentially to a firing chamber or barrel. An opening is provided in the magazine so as to release back-pressure. Paint balls are fed into the firing chamber through the magazine in a direction tangent to the firing chamber and in a direction perpendicular to the radial direction of the firing chamber or barrel. The paint balls being loaded into the firing chamber each have a limited radial distance to travel and therefore have a limited travel period. The unique configuration enables each paint ball being loaded into the chamber to come to rest in the firing chamber more rapidly and thereby reduces the risk of the gun becoming jammed. Further, this configuration enables the gun to be fired more rapidly and with greater assurance that the gun will not jam.

Abstract: A patient lift assembly is provided in which a patient supported on a sheet of flexible, durable material is elevated by increasing the horizontal distance between elevated horizontal arms to which the sheet is removably attached. The horizontal distance between the arms is increased by increasing the distance between the base leg connectors of the apparatus which, in turn, separates the uprights to which the arms are attached. The patient is lowered by decreasing the distance between the arms and increasing the slack in the sheet.