Patents by Inventor John P. Leon

John P. Leon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field programmable gate array incorporating dedicated memory stacks
    Patent number: 7265579
    Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 4, 2007
    Assignee: Irvine Sensors Corp.
    Inventors: Randolph Stuart Carlson, Volkan Ozguz, Keith D. Gann, John P. Leon
  • Field programmable gate array with a variably wide word width memory
    Patent number: 6856167
    Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 15, 2005
    Assignee: Irvine Sensors Corporation
    Inventors: Volkan H. Ozguz, Randolph S. Carlson, Keith D. Gann, John P. Leon
  • Field programmable gate array with a variably wide word width memory
    Publication number: 20030223295
    Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m×N where m is the number of word width bits per memory chip and N is the number of memory chips.
    Type: Application
    Filed: January 17, 2003
    Publication date: December 4, 2003
    Inventors: Volkan H. Ozguz, Randolph S. Carlson, Keith D. Gann, John P. Leon