Abstract: The present invention provides systems and methods for communication system control utilizing corrected forward error correction (FEC) error location identifiers in multi-level modulation scheme systems. The present invention utilizes precise error correction information, available for each FEC block of a particular code (including, but not limited to, block codes and concatenated block codes employing iterative decoding as well as convolutional codes (including turbo codes) and low-density parity-check code (LDPC) class codes) used (e.g., Bose, Ray-Chaudhuri, Hocquenghem (BCH), Reed-Solomon, etc.), as a result of the FEC decoding process to provide feedback to close the loop for control of a demodulator (i.e., receiver). Each error location can be uniquely traced back to a particular sub-rate signal path, with running, post-FEC corrected BER (bit error rate) calculations generated on each sub-rate signal.

Abstract: The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing network-induced clock jitter and wander that occurs in a transport network during asynchronous mapping techniques, bit and/or byte-stuffing techniques, or traditional pointer adjustment schemes associated with traditional PDH (pleisiosynchronous digital hierarchy), SDH (synchronous digital hierarchy), and packet-based networks. The timing recovery circuit may be implemented in a logic circuit such as programmable, digital FPGA (field programmable gate array) logic, or alternatively in standard cell or gate-array ASIC (application-specific integrated circuit) technology, or like logic circuit design.

Abstract: The present invention provides frame-interleaving systems and methods for Optical Transport Unit K (OTUK) (i.e. Optical Transport Unit 4 (OTU4)), 100 Gb/s Ethernet (100 GbE), and other 100 Gb/s (100 G) optical transport enabling multi-level optical transmission. The frame-interleaving systems and methods of the present invention support the multiplexing of sub-rate clients, such as 10×10 Gb/s (10 G) clients, 2×40 Gb/s (40 G) plus 2×10 G clients, etc., into two 50 Gb/s (50 G) transport signals, four 25 Gb/s (25 G) transport signals, etc. that are forward error correction (FEC) encoded and carried on a single wavelength to provide useful, efficient, and cost-effective 100 G optical transport solutions today. In one exemplary configuration, a 100 G client signal or 100 G aggregate client signal carried over two or more channels is frame-deinterleaved, followed by even/odd sub-channel FEC encoding and framing.

Abstract: The present invention provides byte-interleaving systems and methods for Optical Transport Unit N (OTUN) (i.e. Optical Transport Unit 4 (OTU4)) and 100 Gb/s (100 G) optical transport enabling multi-level optical transmission. The byte-interleaving systems and methods of the present invention support the multiplexing of sub-rate clients, such as 10 Gb/s (10 G) clients, 40 Gb/s (40 G) clients, etc., into two 50 Gb/s (50 G) logical flows, for example, that can be forward error correction (FEC) encoded and carried on a single wavelength to provide useful, efficient, and cost-effective 100 G optical transport today. Signaling format support allows these two 50 G logical flows to be forward compatible with an evolving OTU4 and 100 G signaling format without waiting for optical and electronic technology advancement. Signaling format support also allows an evolving standard 100 G logical flow (i.e. OTU4, 100 Gb/s Ethernet (100 GbE), etc.

Abstract: The present invention provides systems and methods for communication system control utilizing corrected forward error correction (FEC) error location identifiers in multi-level modulation scheme systems. The present invention utilizes precise error correction information, available for each FEC block of a particular code (including, but not limited to, block codes and concatenated block codes employing iterative decoding as well as convolutional codes (including turbo codes) and low-density parity-check code (LDPC) class codes) used (e.g., Bose, Ray-Chaudhuri, Hocquenghem (BCH), Reed-Solomon, etc.), as a result of the FEC decoding process to provide feedback to close the loop for control of a demodulator (i.e., receiver). Each error location can be uniquely traced back to a particular sub-rate signal path, with running, post-FEC corrected BER (bit error rate) calculations generated on each sub-rate signal.

Abstract: The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.

Abstract: The present invention provides a high-speed 100G optical transceiver for InfiniBand and Ethernet with associated mapping to frame InfiniBand and Ethernet into GFP-T. The optical transceiver utilizes an architecture which relies on standards-compliant (i.e., multi-sourced) physical client interfaces. These client interfaces are back-ended with flexible, programmable Field Programmable Gate Array (FPGA) modules to accomplish either InfiniBand or Ethernet protocol control, processing, re-framing, and the like. Next, signals are encoded with Forward Error Correction (FEC) and can include additional Optical Transport Unit (OTU) compliant framing structures. The resulting data is processed appropriately for the subsequent optical re-transmission, such as, for example, with differential encoding, Gray encoding, I/Q Quadrature encoding, and the like. The data is sent to an optical transmitter block and modulated onto an optical carrier. Also, the same process proceeds in reverse on the receive side.

Abstract: The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing network-induced clock jitter and wander that occurs in a transport network during asynchronous mapping techniques, bit and/or byte-stuffing techniques, or traditional pointer adjustment schemes associated with traditional PDH (pleisiosynchronous digital hierarchy), SDH (synchronous digital hierarchy), and packet-based networks. The timing recovery circuit may be implemented in a logic circuit such as programmable, digital FPGA (field programmable gate array) logic, or alternatively in standard cell or gate-array ASIC (application-specific integrated circuit) technology, or like logic circuit design.