Abstract: A method for automatically defining a query interface for a datamart is described. The datamart includes fact and dimension tables. The method comprises accessing a schema description and a query interface description for the datamart. The schema description specifies a schema, which in turn, defines the relationships between the fact tables and dimension tables of the datamart. The query interface description specifies the fields, related to the schema description, that can be used in a query and the way in which results are to be presented to the user. The fields correspond to columns and rows in the fact tables. The schema description is used to create a first set of commands to create and populate the fact and dimension tables. Additionally, a second set of commands to create the query interface is created. Some commands of the first set of commands are executed causing the creation and population of the tables.

Abstract: A method for automatically defining aggregates for use in a datamart is described. The datamart includes fact and dimension tables. The method comprises accessing a schema description and an aggregates description for the datamart. The schema description specifies a schema, which in turn, defines the relationships between the fact tables and dimension tables of the datamart. The aggregates description specifies the aggregates, which define, from the schema definition, which aggregate tables are to be created from the fact tables and dimension tables in the datamart. The data in the aggregates correspond to the pre-computed results of specific types of queries. In response to a query, the aggregates can be searched to determine an appropriate aggregate to use in response to that query. The schema description is used to create a first set of commands to create and populate the fact and dimension tables.

Abstract: A high speed data transfer method and apparatus. A high speed data bus includes separate data transfer and master control bus portions. A system host computer loads a sequence of source and destination addresses corresponding to communications units coupled to the bus into memory in a bus master controller. The bus controller sequences through these address pairs at an aggregate rate greater than at least some of the devices' ability to transfer data to enhance data transmission speed on the bus. Bus cycles are allocated to devices on the bus according to a scheme dependent on those devices ability to utilize the bus. High speed devices are allocated a greater number of bus cycles per unit time than slower devices.