Abstract: Error correction code (ECC) decoding architecture design using synthesis-time design parameters. An approach is presented herein by which an ECC decoding architecture can be designed using synthesis-time design parameters. The manner presented herein allows for a designer to arrive at an ECC decoding architecture in a more direct, straightforward manner that using prior art means. A number of considerations (e.g., architecture parameters, semi-soft design constraints, parallel implementation, etc.) are initially provided; certain or all of these considerations can be predetermined, determined adaptively, and/or modified during the design process. A designer is provided a means by which a most desirable ECC decoding architecture can be arrived at relatively quickly.

Abstract: Reduced instruction set computer (RISC) processor based disk manager architecture for HDD (Hard Disk Drive) controllers. A means is presented herein by which disk managers operations of a HDD are off-loaded from a main processor to a dedicated RISC processor. The main processor is operable to provide higher level instructions to the RISC processor, and the RISC processor is operable to translate those higher level instructions into bit level instructions that are subsequently provided to one or more control engines that is then operable to execute those bit level instructions to perform one or more channel interfacing protocol control functions that can include any one or more of low level timing for servo demodulation, timing for data formatting operations, media control operations, transfer control operations, and/or other disk manager related functions.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures segregation of scrambled user information, modulation redundancy bits, and RS redundancy bits in such a way that each of the components thereof can be segregated and stored within any desirable digital information memory storage device. By providing this segregated capability, when accessing a portion of a RS codeword from the memory, an entire RS codeword need not be read from the memory. In fact, only the particular field (or bits) needs to be accessed to perform correction thereon. This segregation provides for a reduction in the hardware complexity of translation between user information and a modulation codeword. Also, this segregation provides for the ability to perform correction of only one of the scrambled user information, the modulation redundancy bits, or the RS redundancy bits.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.

Abstract: Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.

Abstract: A system and method identifies and masks physical sectors where the errors encountered during the defect scan exceed a predetermined level. This avoids the need to read and process all the data written to an individual sector during the initial defect scan. This method first writes a predetermined pattern such as a 2-T pattern to the magnetic media available for user data. This written pattern is then read. As the pattern is read, an error result increments or decrements a counter based on the error. The counter reaching a predetermined level signifies that there are too many errors in this physical sector. This sector may then be added to the primary defect list and masked out without reading the remaining written pattern within the sector. This will result significant time savings as physical sectors containing multiple errors are identified without process all the information written to the physical sector.

Abstract: Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented within a hard disk drive (HDD). Because of the location in which the disk management operations are supported and performed within the channel circuitry, the interface between the channel circuitry and the controller circuitry can be implemented to support direct memory access (DMA) protocol data transfers and control there between. Because the disk management operations are supported within the channel circuitry, as opposed to the controller circuitry, then the disk management operations need not necessarily comply with an interface between the channel circuitry and the controller circuitry. This allows for better control of the disk management operations as well as a much broader range and type of interface that can be employed for the interface between the two circuitries.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.