Abstract: A frequency oscillator and a frequency multiplier multiplying the signals from the oscillator contain inherent phase noise. A phase noise canceller removes phase noise, due to both the oscillator and the multiplier, by inserting a delay in one path and comparing phases of the delayed signal and the undelayed signal. This comparison may be either fed back to the tuning port of the oscillator or fed forward to a phase shifter which shakes off the phase noise. The delay may include a delay line, a cavity or any other suitable device which produces a phase shift. The phase noise canceller may also be designed to remove the total phase noise of the system, including additive phase noise from sources other than the oscillator and multiplier. The canceller may be calibrated and may be designed to reduce periodic response thereof.

Abstract: A low cost direct frequency synthesizer is structured to operate with moderate bandwidth, good noise performance, superior spurious performance, and fast switching. The direct frequency synthesizer employs a starter frequency signal f.sub.o (33-1) and a set of LO frequency signals f.sub.1 through f.sub.n (35-1) spaced from each other by a frequency increment .delta.. A mixer circuit (34-1) generates a product of the starter frequency signal and the LO frequency signals. A divider (31-1) has a divider ratio equal to N. The number of LO frequency signals is equal to or less than N. The starter frequency f.sub.o has a value equal to .delta. times (N+x) where x is equal to 0 or a positive integer. The LO frequency f.sub.1 has a value equal to (N+1)f.sub.o. An intermediate nonswitchable band pass filter (36-1) passes a difference portion of the mixer product to the divider, and a nonswitchable output band pass filter (38-1) receives an output from the divider to generate a moderate bandwidth output.

Abstract: A direct frequency synthesizer is provided with a single stage or multiple cascaded stages. Each stage includes a fixed frequency input channel and a selectable frequency input channel which are coupled respectively to the I and L ports of a mixer. The input channel includes a divider having a divisor equal to N. The selectable frequencies range from f.sub.1 to f.sub.1 +j.theta.. Single-pole-multiple-throw switches selectively connect the fixed and selectable frequencies to the mixer to generate output frequency signals through an output filter bank. Specific relationships among N, n and .theta. are used to establish continuous output frequency coverage, stage cascadability and other synthesizer operating features.

Abstract: A system for comparing the frequency of a voltage controlled oscillator to a stable reference oscillator to generate control signals which maintain the voltage controlled oscillator in phase lock with the reference oscillator. The circuit utilizes a digital frequency comparator to determine whether the output frequency of the voltage controlled oscillator is above or below the reference frequency. When the frequency of the oscillator is either above or below the desired value, pulses are generated which are integrated to produce a DC signal which changes the frequency of the oscillator to achieve the desired value. Additionally, a continuous electrical signal is generated when the output of the voltage controlled oscillator is in phase with the reference signal. When phase lock is achieved the output of the frequency determining circuit goes to zero and phase lock is maintained by the continuous electrical signal.

Abstract: A digitally controlled microwave phase lock loop for switching rapidly from one lock frequency to another is disclosed. A digital word corresponding to a desired input voltage for a selected frequency is converted to an analog voltage for application to the coarse tuning port of the loop's voltage controlled oscillator. Prior to switching to another frequency, the error voltage for the fine tuning port is compared with a zero error reference voltage. The least significant bit of the digital word for such frequency is increased or decreased by one depending on the direction difference between the compared voltages. This incrementally changed word controls the coarse tuning voltage during the next selection of the particular frequency. The system is initialized by repetitively selecting each of the possible frequencies until the digital word for each selected frequency is within one increment of the zero error reference voltage for the fine tuning port.

Abstract: A vibration noise filtering system for use in airborne radar master oscillator, RMO, systems is disclosed. Master and slave crystal oscillators are used, the slave oscillator being phase locked to the master oscillator governed by a phase locked loop, PLL, having a predetermined low frequency bandwidth. The master oscillator is structurally coupled directly to a source of vibration of the aircraft, while the slave oscillator is isolated and supported from the vibration source by a mechanical passive isolator having a resonant frequency well within the low frequency bandwidth of the PLL. The output of the slave oscillator which is the source of the RMO signal has a phase spectral density within the phase stability requirements of a typical RMO across the operating modulating frequency ranges of both air-to-ground and air-to-air radar modes.