Abstract: An apparatus and method are provided for equalizing a dispersive channel based on in-phase and quadrature samples corresponding to an input signal. An equalizer according to the present invention uses a novel adaptation algorithm to adjust filtering characteristics based on previous in-phase samples and a current quadrature sample. The adaptation algorithm is configured to update filter coefficients in response to detecting a transition in the in-phase samples. The equalizer provides equalization for quadrature post-cursor intersymbol interference (ISI) components of the input signal. In an embodiment, the equalizer also provides equalization for in-phase post-cursor ISI components, quadrature precursor ISI components, in-phase precursor ISI components, or a combination of the forgoing.

Abstract: A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

Abstract: A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.