Patents by Inventor John P. Reifenberg

John P. Reifenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9691849
    Abstract: Under one aspect, a plurality of silicon nanostructures is provided. Each of the silicon nanostructures includes a length and a cross-section, the cross-section being substantially constant along the length, the length being at least 100 microns. Under another aspect, a method of making nanostructures is provided that includes providing a silicon wafer including a thickness and first and second surfaces separated from one another by the thickness; forming a patterned layer of metal on the first surface of the silicon wafer; generating a current through the thickness of the silicon wafer, the metal oxidizing the silicon wafer in a region beneath the patterned layer of the metal; and exposing the silicon wafer to an etchant in the presence of the current, the etchant removing the oxidized region of the silicon wafer so as to define a plurality of nanostructures. Methods of transferring nanowires also are provided.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 27, 2017
    Assignee: Alphabet Energy, Inc.
    Inventors: Jeffrey M. Weisse, John P. Reifenberg, Lindsay M. Miller, Matthew L. Scullin
  • Publication number: 20160190420
    Abstract: Under one aspect, a structure includes a tetrahedrite substrate; a first contact metal layer disposed over and in direct contact with the tetrahedrite substrate; and a second contact metal layer disposed over the first contact metal layer. A thermoelectric device can include such a structure. Under another aspect, a method includes providing a tetrahedrite substrate; disposing a first contact metal layer over and in direct contact with the tetrahedrite substrate; and disposing a second contact metal layer over the first contact metal layer. A method of making a thermoelectric device can include such a method.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 30, 2016
    Inventors: Lindsay Miller, John P. Reifenberg, Douglas Crane, Adam Lorimer, Mario Aguirre, Jordan Chase, Matthew L. Scullin
  • Publication number: 20160035829
    Abstract: Under one aspect, a plurality of silicon nanostructures is provided. Each of the silicon nanostructures includes a length and a cross-section, the cross-section being substantially constant along the length, the length being at least 100 microns. Under another aspect, a method of making nanostructures is provided that includes providing a silicon wafer including a thickness and first and second surfaces separated from one another by the thickness; forming a patterned layer of metal on the first surface of the silicon wafer; generating a current through the thickness of the silicon wafer, the metal oxidizing the silicon wafer in a region beneath the patterned layer of the metal; and exposing the silicon wafer to an etchant in the presence of the current, the etchant removing the oxidized region of the silicon wafer so as to define a plurality of nanostructures. Methods of transferring nanowires also are provided.
    Type: Application
    Filed: April 9, 2015
    Publication date: February 4, 2016
    Inventors: Jeffrey M. Weisse, John P. Reifenberg, Lindsay M. Miller, Matthew L. Scullin
  • Publication number: 20130306929
    Abstract: A multilayer-stacked phase change memory (PCM) device is provided that includes a substrate that is electrically insulative and thermally conductive, a number (n) of PCM layers deposited on the substrate, where each PCM layer is thicker than a previous PCM layer, a number (n?1) layers of passivation layer deposited between the PCM layers, where the (n) PCM layers, and the (n?1) passivation layers form a stacked multi-layer PCM on the substrate, a first electrode deposited on a first side of the multi-layer PCM stack, and a second electrode deposited on a second side of the multi-layer PCM stack, where the first side is opposite the second side, where charge transport is decoupled by stacking the PCM layers with the pasivation layers.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Inventors: Jaeho Lee, John P. Reifenberg, Mehdi Asheghi, Kenneth E. Goodson, H.S. Philip Wong, SangBum Kim