Abstract: An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.

Abstract: An array processor operating in the forced I/O mode includes a master controller (12) for generating sequenced commands for output to slave address generators (52) (54) and (62). The slave (52) and (54) operate in a data processing and a forced I/O mode. Each of the slaves have a set of data instructions and a set of I/O instructions therein. The data instructions are sequenced through in accordance with the sequenced commands generated by the master controller (12) synchronously and in parallel with the other slaves to generate addresses for memories (76) and (80). The master controller (12) initiates the I/O mode with runs independent and asychronously with respect to the sequenced commands to interface with an external I/O device (98). This data is transferred to the associated data memory and, when full, the operation alternates such that the other slave is in the I/O mode and the other data memory is utilized for storing I/O data.