Abstract: In one embodiment, a method is provided. The method comprises analyzing a first code, and generating a second code based on the first code, the second code including a microarchitecture implementation-specific alternative representation of at least some portions of the first code.

Abstract: A method and apparatus for prefetching based upon type identifier tags in an object-oriented programming environment is disclosed. In one embodiment, a register tag including a type identifier and a word count in a cache line may be used to populate a prefetch prediction table. The table may be used to determine correlation between fetches initiated by pointers, and may be used to prefetch to the address pointed to by the value at the word count after a fetch to the address pointed to by the type identifier.

Abstract: A method for generating instructions to facilitate control-quasi-independent-point multithreading is provided. A spawn point and control-quasi-independent-point are determined. An instruction stream is generated to partition a program so that portions of the program are parallelized by speculative threads. A method of performing control-quasi-independent-point guided speculative multithreading includes spawning a speculative thread when the spawn point is encountered. An embodiment of the method further includes performing speculative precomputation to determine a live-in value for the speculative thread.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: In one embodiment a thread management method identifies in a main program a set of instructions that can be dynamically activated as speculative precomputation threads. A wait/sleep operation is performed on the speculative precomputation threads between thread creation and activation, and progress of non-speculative threads is gauged through monitoring a set of global variables, allowing the speculative precomputation threads to determine its relative progress with respect to non-speculative threads.

Abstract: The invention provides a method comprising monitoring an indicator indicating a usage of data speculatively loaded by a processor as a result of executing a speculative instruction; and selectively executing said speculative instruction when it is next encountered as an instruction pointer based on said usage. According to another embodiment, the invention provides a processor comprising a monitoring mechanism to monitor an indicator indicating a usage of data speculative loaded by said processor as a result of executing a speculative instruction; and a speculation control mechanism to selectively execute said speculative instruction when it is next encountered at an instruction pointer based on said usage.

Abstract: The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.

Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

Abstract: A method and apparatus for predicting instruction results in a program using the compiler are described. In one embodiment, the method includes creating a data flow graph associated with the program, identifying a target instruction that is to be executed after a producer instruction, and determining that the outcome of the target instruction is dependent on the outcome of the producer instruction using the data flow graph. The outcome of the producer instruction represents a key into a software structure that includes a set of keys and a corresponding set of predicted outcomes of the target instruction. The method further includes inserting an additional instruction that will retrieve a predicted outcome of the target instruction from the software structure based on the outcome of the producer instruction. The additional instruction will be executed after the producer instruction and before the target instruction.

Abstract: An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The microarchitecture processes descriptors of trace sequences in program order so as to locate and dispatch descriptors of dependence chains that are used to fetch and execute the instructions of the dependence chain in data flow order.

Abstract: A system and method of storing instructions is disclosed. First an instruction is received. Then if the instruction will be used in a next instruction cycle, the instruction is loaded in a next instruction cycle cache memory.

Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract: Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main thread. The burden of spawning threads may fall on the main thread via basic triggers. The speculative threads may also spawn other speculative threads via chaining triggers.

Abstract: A testable integrated circuit contains additional circuitry which defines--when operable in a test mode--a plurality of scan paths in each of which are connected in series a plurality of bistable elements (specifically, special scan path flip-flops) isolated from the integrated circuit combinational circuits. The input and output ends of these scan paths are connected by multi-level demultiplexer and multiplexer arrangements with the input and output pins, respectively, of the integrated circuit. The last level demultiplexer and the last level multiplexer include first groups of connections with the input and output ends of the scan paths, respectively, and second groups of connections with the input and output ends of the mission logic. The demultiplexers, the multiplexers and the scan path flip-flops are operable between mission and test modes upon the application of a mode control signal thereto.