Patents by Inventor John P. Short

John P. Short has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5334273
    Abstract: A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100.degree. C. to make the slices pliable so as to comply with each other during the bonding step.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: August 2, 1994
    Assignee: Harris Corporation
    Inventors: John P. Short, Craig J. McLachlan, George V. Rouse, James R. Zibrida
  • Patent number: 5266135
    Abstract: A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100.degree. C. to make the slices pliable so as to comply with each other during the bonding step.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: November 30, 1993
    Assignee: Harris Corporation
    Inventors: John P. Short, Craig J. McLachlan, George V. Rouse, James R. Zibrida
  • Patent number: 4851078
    Abstract: A method of forming a high quality dielectrically isolated silicon on insulator semiconductor device using a double wafer bonding process. As a result of the double wafer bonding process, the invention significantly reduces the device limitations presently known with dielectric isolation and silicon on insulator structures. The present invention specifically eliminates the need for grinding or polishing the final surface which the devices will be implemented in, thereby eliminating the adverse effects which these mechanical processes impute onto these surfaces. Additionally, the present invention eliminates the need for a thick polycrystalline deposition for the production of the dielectric isolation, thereby eliminating the adverse effects of single crystal bulk defects and the loss of tolerance control due to warpage which would otherwise occur in a dielectric isolated process.
    Type: Grant
    Filed: June 29, 1987
    Date of Patent: July 25, 1989
    Assignee: Harris Corporation
    Inventors: John P. Short, George V. Rouse
  • Patent number: 4554059
    Abstract: Plane indicating moats are formed extending through an epitaxial layer into a substrate simultaneous with the formation of the isolation moats which terminate within the epitaxial layer. The substrate is ground to a predetermined thickness after formation of the dielectric isolation and support structure. The composite structure is inserted in an etchant with conditions set to electrochemically etch only the substrate. The exposed plane indicating moats are used as a reference for a final polishing step.
    Type: Grant
    Filed: December 4, 1984
    Date of Patent: November 19, 1985
    Assignee: Harris Corporation
    Inventors: John P. Short, Craig J. McLachlan, Charles Messmer, Paul S. Reinecke
  • Patent number: D353871
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: December 27, 1994
    Inventor: John P. Short