Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.

Abstract: A request to access data at a first physical address misses in a private cache of a processor. A confidence value is received for the first physical address based on a hash value of the first physical address. A determination is made that the received confidence value exceeds a threshold value. In response, a speculative read request specifying the first physical address is issued to a memory controller of a main memory to expedite a miss for the data at the first physical address in a shared cache.

Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.

Abstract: A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.

Abstract: A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.

Abstract: Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.

Abstract: Systems, methods, and computer-readable storage media for predicting escalation risks in customer support contexts. A system implementing the example method can identify instances of customer escalation from a corpus of customer support sales, customer support, and product software development data, and determine, for the instances of customer escalation, sets of trigger conditions that were at least partially responsible for respective instances of customer escalation. Then the system can classify each of the instances of customer escalation by problem type based on the set of trigger conditions to yield classifications, and add the classifications, the sets of trigger conditions, and the instances of customer escalation to a database. Then the system can compare the database to support data to identify customers or support tasks that are likely to be escalated, and the system or a user can allocate additional support resources to proactively prevent escalations.

Abstract: Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution is disclosed. In one aspect, an adaptive cache prefetch circuit is provided for prefetching data into a cache. The adaptive cache prefetch circuit is configured to determine which prefetch policy to use as a replacement policy based on competing dedicated prefetch policies applied to dedicated cache sets in the cache. Each dedicated cache set has an associated dedicated prefetch policy used as a replacement policy for the given dedicated cache set. Cache misses for accesses to each of the dedicated cache sets are tracked by the adaptive cache prefetch circuit. The adaptive cache prefetch circuit can be configured to apply a prefetch policy to the other follower (i.e., non-dedicated) cache sets in the cache using the dedicated prefetch policy that incurred fewer cache misses to its respective dedicated cache sets to reduce cache pollution.

Abstract: Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for analyzing source code and identifying potential defects. The methods employ both static analysis and dynamic testing to detect program defects early in the development stage for better quality with less cost. The analysis also ranks identified potential defects and reports only the most likely defects to a human developer. Once defects are detected, they can be removed right away and similar defects can be prevented automatically.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for analyzing source code and identifying potential defects. The methods employ both static analysis and dynamic testing to detect program defects early in the development stage for better quality with less cost. The analysis also ranks identified potential defects and reports only the most likely defects to a human developer. Once defects are detected, they can be removed right away and similar defects can be prevented automatically.