Patents by Inventor John Pane

John Pane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160316048
    Abstract: A telephone headset is provided which includes a presence status indicator thereon for signaling to other persons the user's availability and/or willingness to communicate face-to-face.
    Type: Application
    Filed: July 6, 2016
    Publication date: October 27, 2016
    Inventors: Philip John Pane, Thomas F. Terrien, JR., David Alden Jaques, William J. Blank, JR., Brian J. Cole
  • Patent number: 9413790
    Abstract: A telephone headset is provided which includes a presence status indicator thereon for signaling to other persons the user's availability and/or willingness to communicate face-to-face.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 9, 2016
    Assignee: VXi Corporation
    Inventors: Philip John Pane, Thomas F. Terrien, Jr., David Alden Jaques, William J. Blank, Jr., Brian J. Cole
  • Publication number: 20140153405
    Abstract: A telephone headset is provided which includes a presence status indicator thereon for signaling to other persons the user's availability and/or willingness to communicate face-to-face.
    Type: Application
    Filed: August 30, 2013
    Publication date: June 5, 2014
    Applicant: VXI Corporation
    Inventors: Philip John Pane, Thomas F. Terrien, JR., David Alden Jaques, William J. Blank, JR., Brian J. Cole
  • Patent number: 7668235
    Abstract: A method of jitter measurement is provided and includes sampling a device-under-test (DUT) output signal, having a repeating pattern, using an asynchronous clock over a desired period of time and mapping the samples onto a single period of the repeating pattern. Each period of the repeating pattern is sampled at least twice. A sampling frequency of the asynchronous clock is based on user inputs. Sampling the DUT signal comprises capturing logical state information representing each edge of a single period of the DUT signal at least once. The method further includes, separating the samples into subsets and mapping the sample subsets onto a single period of the repeating pattern wherein the samples within a particular subset are mapped to a set of times which are in the same order as in which the samples were obtained, processing the samples within each subset independently of samples in other subsets, and combining results of the processed subsets and processing the combined results of the subsets.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 23, 2010
    Assignee: Teradyne
    Inventors: Michael Panis, Steve Munroe, John Pane
  • Publication number: 20070118315
    Abstract: A method of jitter measurement is provided and includes sampling a device-under-test (DUT) output signal, having a repeating pattern, using an asynchronous clock over a desired period of time and mapping the samples onto a single period of the repeating pattern. Each period of the repeating pattern is sampled at least twice. A sampling frequency of the asynchronous clock is based on user inputs. Sampling the DUT signal comprises capturing logical state information representing each edge of a single period of the DUT signal at least once. The method further includes, separating the samples into subsets and mapping the sample subsets onto a single period of the repeating pattern wherein the samples within a particular subset are mapped to a set of times which are in the same order as in which the samples were obtained, processing the samples within each subset independently of samples in other subsets, and combining results of the processed subsets and processing the combined results of the subsets.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 24, 2007
    Applicant: Teradyne, Inc.
    Inventors: Michael Panis, Steve Munroe, John Pane
  • Publication number: 20060116840
    Abstract: A method and system is provided for detecting and correcting non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs. The automatic test apparatus and method can correct non-determinism caused by cycle slipping at the beginning of data transmission, between packets of data being transmitted and out-of-order data types of non-determinism. A data validation circuit is coupled to the receiver for validating the packet data based on expected packet data stored in a vector memory.
    Type: Application
    Filed: October 25, 2005
    Publication date: June 1, 2006
    Inventors: Jonathan Hops, Brian Swing, John Pane, Bruce Sudweeks, Brian Phelps, James Kinslow
  • Patent number: 6990423
    Abstract: Automatic test equipment for testing non-deterministic packet data from a device-under-test is disclosed. The automatic test equipment includes a memory for storing expected packet data and a receiver for receiving the packet data from the device-under-test. A data validation circuit is coupled to the receiver for validating non-deterministic packet data based on the expected packet data from the vector memory.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: January 24, 2006
    Assignee: Teradyne, Inc.
    Inventors: Benjamin Brown, Peter Huber, Mark Donahue, John Pane
  • Publication number: 20040267487
    Abstract: Automatic test equipment for testing non-deterministic packet data from a device-under-test is disclosed. The automatic test equipment includes a memory for storing expected packet data and a receiver for receiving the packet data from the device-under-test. A data validation circuit is coupled to the receiver for validating non-deterministic packet data based on the expected packet data from the vector memory.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Inventors: Benjamin Brown, Peter Huber, Mark Donahue, John Pane