Abstract: An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.

Abstract: A system for performing analog-to-digital conversion comprises a sampling unit that generates multiple digital samples from an analog input signal at each recurrence of a periodic interval, and a processing unit that combines the digital samples to produce a digital output signal. In certain embodiments, the sampling unit comprises multiple analog-to-digital converters arranged in parallel, and the processing unit comprises a digital signal processor that detects outliers in the digital samples and averages any non-outliers among the digital samples to generate the digital output signal.

Abstract: A clock recovery circuit includes a phase detector, a loop filter, a phase rotator, a predictor and a delay line. The phase detector receives an input data signal and generates a phase error signal for estimating phase error in the input data signal when referred to a recovered clock. The loop filter receives the phase error signal and determines a phase control signal based on the phase error signal. The phase rotator receives the phase control signal, and provides a phase adjusted clock based on a reference clock and the phase control signal. The predictor receives the phase error signal, and determines a delay control signal based on the phase error signal. The delay line outputs the recovered clock by delaying the phase adjusted clock from the phase rotator using the delay control signal from the predictor, and provides the recovered clock to the phase detector.

Abstract: A system for performing analog-to-digital conversion comprises a sampling unit that generates multiple digital samples from an analog input signal at each recurrence of a periodic interval, and a processing unit that combines the digital samples to produce a digital output signal. In certain embodiments, the sampling unit comprises multiple analog-to-digital converters arranged in parallel, and the processing unit comprises a digital signal processor that detects outliers in the digital samples and averages any non-outliers among the digital samples to generate the digital output signal.

Abstract: An approach is provided that receives web page data at a network adapter included in an information handling system. A process identifies a first set style sheets that apply to the web page data and a second set of style sheets that apply to graphical elements that are within a predefined proximity area of a cursor that is displayed on the information handling system's display screen. The process displays graphical elements that are outside the predefined proximity area using the first set of style sheets and simultaneously displays a second set of elements that are within the predefined proximity area using the second set of style sheets.

Abstract: An approach is provided that receives web page data at a network adapter included in an information handling system. A process identifies a first set style sheets that apply to the web page data and a second set of style sheets that apply to graphical elements that are within a predefined proximity area of a cursor that is displayed on the information handling system's display screen. The process displays graphical elements that are outside the predefined proximity area using the first set of style sheets and simultaneously displays a second set of elements that are within the predefined proximity area using the second set of style sheets.

Abstract: A phase-locked loop circuit comprises an analog section, a digital section and a digital offset mitigation circuit. The analog section is subject to offset error and comprises an analog phase comparator and an analog-to-digital converter. The digital section comprises a digital loop filter and a digitally-controlled frequency-generating circuit. The digital loop filter is connected to receive a digital difference signal from the analog-to-digital converter. The digital offset mitigation circuit is operable in response to the digital difference signal to mitigate the offset error of the analog section.