Abstract: A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5).

Abstract: A method for converting multi-bit digital video data signals to analogue form wherein the video data signals are in three formats, namely, standard definition, progressive scan and high definition formats, which permits a relatively low order analogue reconstruction filter to be used for filtering the analogue form of the signal. The three formats of the digital video data signals are over-sampled at relatively low over-sampling rates, the standard definition video signals being over-sampled at eight times the nyquist sampling frequency, the progressive scan format signals being over-sampled at four times the nyquist sampling frequency, while the high definition format signals are over-sampled at twice the nyquist sampling frequency.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimised. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimising crosstalk between the DACs (5).

Abstract: A video signal processor (1) for converting standard definition and progressive scan video data signals from digital form to analogue form comprises a video signal processing circuit (7) in which the signals are converted. The respective standard and progressive video data signals are received on first and second clock signals CLOCK—1 and CLOCK—2, respectively, which are of identical frequency and have a constant phase relationship. An interface circuit (10) for interfacing the standard definition and progressive scan video data signals with the video signal processor (7) comprises a first register (20) into which the progressive scan signal is clocked on the second clock signal CLOCK—2. The progressive scan signal is clocked from the first register (20) to a second register (21) by the first clock signal CLOCK—1 and in turn from the second register (21) to a third register (22) by the first clock signal CLOCK—1.

Abstract: A method for converting multi-bit digital video data signals to analogue form wherein the video data signals are in three formats, namely, standard definition, progressive scan and high definition formats, which permits a relatively low order analogue reconstruction filter to be used for filtering the analogue form of the signal. The three formats of the digital video data signals are over-sampled at relatively low over-sampling rates, the standard definition video signals being over-sampled at eight times the nyquist sampling frequency, the progressive scan format signals being over-sampled at four times the nyquist sampling frequency, while the high definition format signals are over-sampled at twice the nyquist sampling frequency.

Abstract: A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high.